Datasheet ZSSC3240 (Renesas) - 9
| Manufacturer | Renesas |
| Description | Sensor Signal Conditioner IC for Resistive Sensors |
| Pages / Page | 64 / 9 — ZSSC3240. Symbol. Parameter. Conditions. Minimum. Typical. Maximum. … |
| Revision | 20200414 |
| File Format / Size | PDF / 1.2 Mb |
| Document Language | English |
ZSSC3240. Symbol. Parameter. Conditions. Minimum. Typical. Maximum. Units. Sensor Supply. Analog-to-Digital Converter (ADC, A2D)
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ZSSC3240 Symbol Parameter Conditions Minimum Typical Maximum Units
Average current draw Mean current consumption for one – – 3.5 µA IAVE complete SSC measurement cycle per second at 16-bit digital-only output Target level regulation Using LDOctrl and external transistor; 4.6 5.2 5.5 V range to generate V programmable setup: VDD_ldoctrl_target V DD DD,LDOctrl after external transistor, (see section 6.7) for example JFET
Sensor Supply
ISUP Sensor bias In the case of a Current Mode sensor 5 80 500 µA Relative sensor bias supply; setup in temp_source and -3.5 -1 1.5 % ErrTBIAS current error [a] sensor_sup (see section 6.2) Drop over sensor bias referenced VDDA – 200 230 mV V int from internal analog TBIAS current source regulator Internally regulated In the case of a ratiometric sensor 1.68 1.75 1.80 V VDDB analog (bridge) sensor supply, setup in temp_source and (VDDAint) front-end supply sensor_sup Power supply rejection Attenuation of V 45 50 – dB PSRR DD fluctuations in the LOW ratio[b], only internal range of fVDD = 0Hz to 10MHz PSRR regulator HIGH fVDD > 10MHz 20 – – dB
Analog-to-Digital Converter (ADC, A2D)
rADC Resolution 12 16 24 Bit Single-conversion rate, Single external sensor A2D conversion 0.21 3.39 13.00 kHz fS,raw conversions per second (without auto-zero measurement AZ); (ADC: (ADC: (ADC: resolution dependent 24-bit) 16-bit) 12-bit) Differential ADC input With internal regulator supplying VDDB – 0.5 – VDDB VADCmid common mode [c] pin, typical: VDDB/2 = 875mV (equals (AGND) PGA output common mode level) Effective number of bits, For gain < 78, shorted input, rADC 15.8 18.1 – Bit ENOB [g] = 3σNoise based 24-bit, no oversampling
Digital-to-Analog Converter (DAC) and Analog Output
rDAC Resolution 13 14 16 Bit Analog voltage output Time from 30% steady state until 99% of 0 65 150 µs tDACsettle settling time new DAC output (100% out) value is reached; varies with level differences Absolute output, Aout_setup = 010BIN 0.025 – 1 V (see section 6.5.3.1) Addressable output VDACout Absolute output, V 0.025 – 5 V voltage at AOUT pin DD > 5.01V, Aout_setup = 011BIN Ratiometric output, Aout_setup = 001BIN 0.1 – 100 %VDD BWDAC Output filter bandwidth Without external components 12 15 20 kHz Output slew rate Resistive load > 2kΩ, 20 100 - mV/µs SRout capacitive load < 20nF at Aout, temperature = 25°C Maximum output current This current level must be overdriven 10 12 18 mA from an OWI-Master, if concurrent DAC- IOUTmax output and OWI communication is configured. Current loop driving Aout_setup = 000BIN; depends on IDRloop current connected bipolar transistor for current – 100 160 µA loop application
Programmable-Gain Amplifier (PGA)
Gamp Gain 120 steps 1.32 – 540 V/V Gerr Gain error Referenced to nominal gain, T = 25°C -2.5 0 2.5 % Supported input common VDDA V int = 1.75V, valid for ratiometric and CMin 0.70 0.85 1.00 V mode current mode sensor supply
Sensor Signal Conditioning Performance
Cyclic operation 0.07 1.45 2.91 kHz SSC-corrected (S, T ) digital output rate, – 1.20 – kHz ADC:16-bit (see section 6.6.3.1) fSSCout Output (Update) rate [d] Complete SSC cycle (S, T ) including analog output update; ADC: 14-bit; DAC: 1.35 1.45 1.60 kHz 14-bit Apr.15.20 Page 9 Document Outline 1. Pin Assignments 2. Pin Descriptions 3. Absolute Maximum Ratings 4. Recommended Operating Conditions 5. Electrical Characteristics 6. Device Description 6.1 Signal Flow 6.2 Analog (Sensor) Front-End 6.2.1. Programmable-Gain Amplifier (PGA) 6.2.2. Analog-to-Digital Converter (ADC) 6.2.3. Internal Temperature Sensor 6.2.4. Supported Supplies for Sensor Elements and Additional, External Temperature Sensing 6.3 On-Chip Diagnostics 6.4 Digital Interfaces 6.4.1. SPI 6.4.2. I2C 6.4.3. One-Wire-Interface, OWI 6.5 Measurement and Output Options 6.5.1. Single Measurements, Digital Raw Results, and SSC Results 6.5.2. Cyclic, Continuous, Repeated Measurements – Measurement Scheduler 6.5.3. Analog Outputs: Digital-to-Analog Converter (DAC) 6.5.4. Output Interrupt Signaling 6.6 System Setup and Control 6.6.1. Digital Commands 6.6.2. Nonvolatile Memory (NVM) 6.6.3. Digital Sensor-Signal-Conditioning Mathematics 6.7 External, Extra LDO (LDOctrl) for Applications for > 5.5V 7. Calibration 8. Package Outline Drawings 9. Marking Diagram 10. Ordering Information 11. Glossary 12. Revision History
ZSSC3240 Symbol Parameter Conditions Minimum Typical Maximum Units
Average current draw Mean current consumption for one – – 3.5 µA IAVE complete SSC measurement cycle per second at 16-bit digital-only output Target level regulation Using LDOctrl and external transistor; 4.6 5.2 5.5 V range to generate V programmable setup: VDD_ldoctrl_target V DD DD,LDOctrl after external transistor, (see section 6.7) for example JFET
Sensor Supply
ISUP Sensor bias In the case of a Current Mode sensor 5 80 500 µA Relative sensor bias supply; setup in temp_source and -3.5 -1 1.5 % ErrTBIAS current error [a] sensor_sup (see section 6.2) Drop over sensor bias referenced VDDA – 200 230 mV V int from internal analog TBIAS current source regulator Internally regulated In the case of a ratiometric sensor 1.68 1.75 1.80 V VDDB analog (bridge) sensor supply, setup in temp_source and (VDDAint) front-end supply sensor_sup Power supply rejection Attenuation of V 45 50 – dB PSRR DD fluctuations in the LOW ratio[b], only internal range of fVDD = 0Hz to 10MHz PSRR regulator HIGH fVDD > 10MHz 20 – – dB
Analog-to-Digital Converter (ADC, A2D)
rADC Resolution 12 16 24 Bit Single-conversion rate, Single external sensor A2D conversion 0.21 3.39 13.00 kHz fS,raw conversions per second (without auto-zero measurement AZ); (ADC: (ADC: (ADC: resolution dependent 24-bit) 16-bit) 12-bit) Differential ADC input With internal regulator supplying VDDB – 0.5 – VDDB VADCmid common mode [c] pin, typical: VDDB/2 = 875mV (equals (AGND) PGA output common mode level) Effective number of bits, For gain < 78, shorted input, rADC 15.8 18.1 – Bit ENOB [g] = 3σNoise based 24-bit, no oversampling
Digital-to-Analog Converter (DAC) and Analog Output
rDAC Resolution 13 14 16 Bit Analog voltage output Time from 30% steady state until 99% of 0 65 150 µs tDACsettle settling time new DAC output (100% out) value is reached; varies with level differences Absolute output, Aout_setup = 010BIN 0.025 – 1 V (see section 6.5.3.1) Addressable output VDACout Absolute output, V 0.025 – 5 V voltage at AOUT pin DD > 5.01V, Aout_setup = 011BIN Ratiometric output, Aout_setup = 001BIN 0.1 – 100 %VDD BWDAC Output filter bandwidth Without external components 12 15 20 kHz Output slew rate Resistive load > 2kΩ, 20 100 - mV/µs SRout capacitive load < 20nF at Aout, temperature = 25°C Maximum output current This current level must be overdriven 10 12 18 mA from an OWI-Master, if concurrent DAC- IOUTmax output and OWI communication is configured. Current loop driving Aout_setup = 000BIN; depends on IDRloop current connected bipolar transistor for current – 100 160 µA loop application
Programmable-Gain Amplifier (PGA)
Gamp Gain 120 steps 1.32 – 540 V/V Gerr Gain error Referenced to nominal gain, T = 25°C -2.5 0 2.5 % Supported input common VDDA V int = 1.75V, valid for ratiometric and CMin 0.70 0.85 1.00 V mode current mode sensor supply
Sensor Signal Conditioning Performance
Cyclic operation 0.07 1.45 2.91 kHz SSC-corrected (S, T ) digital output rate, – 1.20 – kHz ADC:16-bit (see section 6.6.3.1) fSSCout Output (Update) rate [d] Complete SSC cycle (S, T ) including analog output update; ADC: 14-bit; DAC: 1.35 1.45 1.60 kHz 14-bit Apr.15.20 Page 9 Document Outline 1. Pin Assignments 2. Pin Descriptions 3. Absolute Maximum Ratings 4. Recommended Operating Conditions 5. Electrical Characteristics 6. Device Description 6.1 Signal Flow 6.2 Analog (Sensor) Front-End 6.2.1. Programmable-Gain Amplifier (PGA) 6.2.2. Analog-to-Digital Converter (ADC) 6.2.3. Internal Temperature Sensor 6.2.4. Supported Supplies for Sensor Elements and Additional, External Temperature Sensing 6.3 On-Chip Diagnostics 6.4 Digital Interfaces 6.4.1. SPI 6.4.2. I2C 6.4.3. One-Wire-Interface, OWI 6.5 Measurement and Output Options 6.5.1. Single Measurements, Digital Raw Results, and SSC Results 6.5.2. Cyclic, Continuous, Repeated Measurements – Measurement Scheduler 6.5.3. Analog Outputs: Digital-to-Analog Converter (DAC) 6.5.4. Output Interrupt Signaling 6.6 System Setup and Control 6.6.1. Digital Commands 6.6.2. Nonvolatile Memory (NVM) 6.6.3. Digital Sensor-Signal-Conditioning Mathematics 6.7 External, Extra LDO (LDOctrl) for Applications for > 5.5V 7. Calibration 8. Package Outline Drawings 9. Marking Diagram 10. Ordering Information 11. Glossary 12. Revision History
