Datasheet AD5592R (Analog Devices) - 8
| Manufacturer | Analog Devices |
| Description | 8 Channel, 12-Bit, Configurable ADC/DAC with on-chip Reference, SPI interface |
| Pages / Page | 43 / 8 — AD5592R. Data Sheet. Table 4. AD5592R-1 T. iming Characteristics … |
| Revision | E |
| File Format / Size | PDF / 984 Kb |
| Document Language | English |
AD5592R. Data Sheet. Table 4. AD5592R-1 T. iming Characteristics Parameter. 1.62 V ≤ VLOGIC < 3 V. 3 V ≤ VLOGIC ≤ 5.5 V. Unit
Model Line for this Datasheet
Text Version of Document
AD5592R Data Sheet Table 4. AD5592R-1 T iming Characteristics Parameter 1.62 V ≤ VLOGIC < 3 V 3 V ≤ VLOGIC ≤ 5.5 V Unit Test Conditions/Comments
t1 33 20 ns min SCLK cycle time, write operation 65 50 ns min SCLK cycle time, read operation t2 16 10 ns min SCLK high time t3 16 10 ns min SCLK low time t4 15 10 ns min SYNC to SCLK falling edge setup time 2 2 µs max SYNC to SCLK falling edge setup time t5 7 7 ns min Data setup time t6 5 5 ns min Data hold time t7 15 10 ns min SCLK falling edge to SYNC rising edge t8 30 30 ns min Minimum SYNC high time for write operations 60 60 ns min Minimum SYNC high time for register read operations t9 0 0 ns min SYNC rising edge to next SCLK falling edge t10 56 25 ns max SCLK rising edge to SDO valid
200µA IOL TO OUTPUT 1.6V PIN CL 25pF
203
200µA IOH
12506- Figure 3. Load Circuit for Logic Output (SDO) Timing Specifications
t1 t9 SCLK t2 t t t3 t 8 4 7 SYNC t6 t5 SDI DB15 DB0 t10
002
SDO DB15 DB0
12506- Figure 4. Timing Diagram Rev. E | Page 8 of 43 Document Outline Features Applications General Description Functional Block Diagram Revision History Functional Block Diagram (AD5592R-1) Specifications Timing Characteristics Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configurations and Function Descriptions Typical Performance Characteristics Terminology ADC Terminology DAC Terminology Theory of Operation DAC Section Resistor String Output Buffer ADC Section Calculating ADC Input Current GPIO Section Internal Reference RESETB Function Temperature Indicator Serial Interface Power-Up Time Write Mode Read Mode Configuring the AD5592R/AD5592R-1 General-Purpose Control Register DAC Write Operation LDAC Mode Operation DAC Readback ADC Operation Changing an ADC Sequence GPIO Operation Setting Pins as Outputs Setting Pins as Inputs Three-State Pins 85 kΩ Pull-Down Resistor Pins Power-Down Mode Reset Function Readback and LDAC Mode Register Applications Information Microprocessor Interfacing AD5592R/AD5592R-1 to SPI Interface AD5592R/AD5592R-1 to SPORT Interface Layout Guidelines Outline Dimensions Ordering Guide
t1 33 20 ns min SCLK cycle time, write operation 65 50 ns min SCLK cycle time, read operation t2 16 10 ns min SCLK high time t3 16 10 ns min SCLK low time t4 15 10 ns min SYNC to SCLK falling edge setup time 2 2 µs max SYNC to SCLK falling edge setup time t5 7 7 ns min Data setup time t6 5 5 ns min Data hold time t7 15 10 ns min SCLK falling edge to SYNC rising edge t8 30 30 ns min Minimum SYNC high time for write operations 60 60 ns min Minimum SYNC high time for register read operations t9 0 0 ns min SYNC rising edge to next SCLK falling edge t10 56 25 ns max SCLK rising edge to SDO valid
200µA IOL TO OUTPUT 1.6V PIN CL 25pF
203
200µA IOH
12506- Figure 3. Load Circuit for Logic Output (SDO) Timing Specifications
t1 t9 SCLK t2 t t t3 t 8 4 7 SYNC t6 t5 SDI DB15 DB0 t10
002
SDO DB15 DB0
12506- Figure 4. Timing Diagram Rev. E | Page 8 of 43 Document Outline Features Applications General Description Functional Block Diagram Revision History Functional Block Diagram (AD5592R-1) Specifications Timing Characteristics Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configurations and Function Descriptions Typical Performance Characteristics Terminology ADC Terminology DAC Terminology Theory of Operation DAC Section Resistor String Output Buffer ADC Section Calculating ADC Input Current GPIO Section Internal Reference RESETB Function Temperature Indicator Serial Interface Power-Up Time Write Mode Read Mode Configuring the AD5592R/AD5592R-1 General-Purpose Control Register DAC Write Operation LDAC Mode Operation DAC Readback ADC Operation Changing an ADC Sequence GPIO Operation Setting Pins as Outputs Setting Pins as Inputs Three-State Pins 85 kΩ Pull-Down Resistor Pins Power-Down Mode Reset Function Readback and LDAC Mode Register Applications Information Microprocessor Interfacing AD5592R/AD5592R-1 to SPI Interface AD5592R/AD5592R-1 to SPORT Interface Layout Guidelines Outline Dimensions Ordering Guide
