Datasheet AD7294-2 (Analog Devices) - 3

Data Sheet AD7294-2 FUNCTIONAL BLOCK DIAGRAM RSENSE TO LOAD AGND1 REF REF OUT/ OUT/ TO DAC OUTV+ AB, VPP1, VPP2 RS1(+) RS1(–) RS2(+) RS2(–) REF REF AV IN ADC IN DAC DD AGND7 DAC OUTV+ CD, HIGH-SIDE HIGH-SIDE 2.5V CURRENT CURRENT REF 100kΩ 200kΩ SENSE SENSE 12-BIT DAC ISENSE2 OVERRANGE V V OUTA REF 10.41 ISENSE1 OVERRANGE 100kΩ 200kΩ OFFSET IN A VIN0 100kΩ 200kΩ V 12-BIT IN1 12-BIT DAC V MUX IN2 ADC VIN3 VOUTB D1(+) D2(+) LIMIT 100kΩ 200kΩ REGISTERS OFFSET IN B 100kΩ 200kΩ 12-BIT T1 T2 DAC D2(–) TEMP V SENSOR OUTC D1(–) 100kΩ 200kΩ OFFSET IN C 100kΩ 200kΩ 12-BIT CONTROL LOGIC AD7294-2 DAC VOUTD I2C INTERFACE PROTOCOL 100kΩ 200kΩ OFFSET IN D
001
DGND (×3) RESET SDA SCL AS2 AS1 AS0 DCAP ALERT/ BUSY
10936- Figure 1. Rev. 0 | Page 3 of 44 Document Outline Features Applications General Description Table of Contents Revision History Functional Block Diagram Specifications DAC Specifications ADC Specifications General Specifications Timing Characteristics I2C Serial Interface Timing and Circuit Diagrams Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Terminology DAC Terminology ADC Terminology Theory of Operation ADC Overview ADC Transfer Functions Analog Inputs Single-Ended Mode Differential Mode Driving Differential Inputs Using an Op Amp Pair Pseudo Differential Mode Current Sensor Choosing RSENSE Current Sense Filtering Kelvin Sense Resistor Connection Analog Comparator Loop Temperature Sensor Remote Sensing Diode Ideality Factor Base Emitter Voltage hFE Variation Series Resistance Cancellation DAC Operation Resistor String Output Amplifiers ADC and DAC Reference VDRIVE Feature Register Settings Address Pointer Register Command Register ADC Result Register ADC Channel Allocation TSENSE1 and TSENSE2 Result Registers TSENSEINT Result Register Temperature Value Format DACA, DACB, DACC, and DACD Value Registers Alert Status Register A, Alert Status Register B, and Alert Status Register C Channel Sequence Register Configuration Register Sample Delay and Bit Trial Delay Power-Down Register DATALOW and DATAHIGH Registers VIN0 to VIN3 Channels TSENSE1, TSENSE2, and TSENSEINT Channels Hysteresis Registers Remote Channel TSENSE1 and TSENSE2 Offset Registers I2C Interface General I2C Timing Serial Bus Address Byte Interface Protocol Writing a Single Byte of Data to an 8-Bit Register Writing Two Bytes of Data to a 16-Bit Register Writing to Multiple Registers Reading Data from an 8-Bit Register Reading Two Bytes of Data from a 16-Bit Register Modes of Operation Command Mode Autocycle Mode Alerts and Limits Theory ALERT_FLAG Bit Alert Status Registers DATALOW and DATAHIGH Monitoring Features Hysteresis Using the Limit Registers to Store Minimum/Maximum Conversion Results Applications Information Base Station Power Amplifier Monitor and Control Gain Control of Power Amplifier Outline Dimensions Ordering Guide