Datasheet AD7292 (Analog Devices) - 4

AD7292 Data Sheet Parameter Min Typ Max Unit Test Conditions/Comments
EXTERNAL REFERENCE Reference Input Voltage 4.75 AVDD V Internal reference used to calibrate temperature sensor Input Resistance 100 kΩ 1 Specifications also apply to differential mode.
DAC SPECIFICATIONS
AVDD = 4.75 V to 5.25 V, DVDD = 1.8 V to 5.25 V, VREF = 1.25 V internal, VDRIVE = 1.8 V to 5.25 V, AGND = 0 V, TA = −40°C to +125°C, unless otherwise noted.
Table 2. Parameter Min Typ Max Unit Test Conditions/Comments
DC ACCURACY Resolution 10 Bits Integral Nonlinearity (INL) ±0.2 ±1 LSB Differential Nonlinearity (DNL) ±0.1 ±0.3 LSB Guaranteed monotonic Zero-Scale Error 4.8 ±10 mV All 0s loaded to DAC register Full-Scale Error ±0.1 ±0.5 % FS All 1s loaded to DAC register Offset Error ±1.62 ±10 mV Measured in the linear region, TA = −40°C to +125°C Offset Error Drift ±4.4 ppm/°C Measured in the linear region, TA = 25°C Gain Error ±0.35 ±0.5 % FS Gain Error Drift ±2.6 ppm/°C DC Power Supply Rejection Ratio (PSRR) −50 dB fRIPPLE up to 100 kHz DC Crosstalk 5 μV DAC OUTPUT CHARACTERISTICS Output Voltage Range 0 4 × VREF V Short-Circuit Current ±30 mA Load Current ±10 mA Sink/source current; within ±200 mV of supply Resistive Load to AGND 500 Ω Capacitive Load Stability 1 nF DC Output Impedance 1 Ω AC CHARACTERISTICS1 Output Voltage Settling Time 1 2 µs ¼ to ¾ scale step change within 1 LSB, measured from last SCLK edge Overshoot 200 mV ¼ to ¾ scale step change within 1 LSB, measured from last SCLK edge; CL = 200 pF, RL = 25 kΩ Slew Rate 9 12 V/µs Digital-to-Analog Glitch Impulse 4 nV-sec Digital Feedthrough 0.4 nV-sec DAC-to-DAC Crosstalk 2 nV-sec Output Noise Spectral Density 730 nV/√Hz DAC code = midscale, 1 kHz Output Noise 28 μV rms 0.1 Hz to 10 Hz Output Transient Response During 5 mV AVDD ramp of 1 ms with 100 kΩ load Power-Up 1 The DAC buffer output level is undefined until 30 µs after all supplies reach their minimum specified operating voltages. Rev. A | Page 4 of 40 Document Outline Features Applications Functional Block Diagram General Description Table of Contents Revision History Specifications ADC Specifications DAC Specifications General Specifications Temperature Sensor Specifications Timing Specifications Timing Diagram Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Theory of Operation Analog Inputs Single-Ended Mode Differential Mode ADC Transfer Functions Temperature Sensor DAC Operation Digital I/O Pins GPIO0/ALERT0 and GPIO1/ALERT1 Pins GPIO2/DAC DISABLE0 and GPIO4/DAC DISABLE1 Pins GPIO3/LDAC Pin GPIO6/BUSY Pin Serial Port Interface (SPI) Interface Protocol Register Structure Register Descriptions Vendor ID Register (Address 0x00) ADC Data Register (Address 0x01) ADC Sequence Register (Address 0x03) Configuration Register Bank (Address 0x05) Digital Output Driver Subregister (Address 0x01) Digital I/O Function Subregister (Address 0x02) General Subregister (Address 0x08) VIN RANGE0 and VIN RANGE1 Subregisters (Address 0x10 and Address 0x11) ADC Sampling Mode Subregister (Address 0x12) VIN Filter Subregister (Address 0x13) Conversion Delay Control Subregister (Address 0x14) VIN ALERT0 Routing and VIN ALERT1 Routing Subregisters (Address 0x15 and Address 0x16) Temperature Sensor Subregister (Address 0x20) Temperature Sensor Alert Routing Subregister (Address 0x21) GPIO2/DAC DISABLE0 and GPIO4/DAC DISABLE1 Subregisters (Address 0x30 and Address 0x31) Alert Limits Register Bank (Address 0x06) Alert High Limit and Alert Low Limit Subregisters Hysteresis Subregisters Alert Flags Register Bank (Address 0x07) ADC Alert Flags and TSENSE Alert Flags Subregisters (Address 0x00 and Address 0x02) Minimum and Maximum Register Bank (Address 0x08) Offset Register Bank (Address 0x09) DAC Buffer Enable Register (Address 0x0A) GPIO Register (Address 0x0B) Conversion Command Register (Address 0x0E) ADC Conversion Result Registers, VIN0 to VIN7 (Address 0x10 to Address 0x17) TSENSE Conversion Result Register (Address 0x20) DAC Channel Registers (Address 0x30 to Address 0x33) ADC Conversion Control ADC Conversion Command ADC Sequencer DAC Output Control LDAC Operation Simultaneous Update of All DAC Outputs Alerts and Limits Alert Limit Monitoring Features Hysteresis Hardware Alert Pins Alert Flag Bits in the Conversion Result Registers Alert Flags Register Bank Minimum and Maximum Conversion Results Outline Dimensions Ordering Guide