Datasheet AD5590 (Analog Devices) - 3

AD5590 GENERAL DESCRIPTION
The AD5590 is a 16-channel input and 16-channel output The DAC section of the AD5590 comprises sixteen 12-bit DACs analog I/O port with eight uncommitted amplifiers, operating divided into two groups of eight. Each group has an on-chip from a single 4.5 V to 5.25 V supply. The AD5590 comprises reference. The on-board references are off at power-up, allowing 16 input channels multiplexed into a 1 MSPS, 12-bit successive the use of external references. The internal references are enabled approximation ADC with a sequencer to al ow a preprogrammed via a software write. selection of channels to be converted sequential y. The ADC The AD5590 incorporates a power-on reset circuit that ensures contains a low noise, wide bandwidth track-and-hold amplifier that the DAC outputs power up to 0 V and remain powered up that can handle input frequencies in excess of 1 MHz. at this level until a valid write takes place. The DAC contains a The conversion process and data acquisition are controlled using power-down feature that reduces the current consumption of ASYNC and the serial clock signal, allowing the device to easily the device and provides software-selectable output loads while interface with microprocessors or DSPs. The input signal is in power-down mode for any or all DAC channels. The outputs sampled on the falling edge of ASYNC and conversion is also of all DACs can be updated simultaneously using the LDAC initiated at this point. There are no pipeline delays associated function, with the added functionality of user-selectable DAC with the ADC. By setting the relevant bits in the control register, channels to simultaneously update. There is also an asynchronous the analog input range for the ADC can be selected to be a 0 V CLR that updates al DACs to a user-programmable code: zero to VREFA input or a 0 V to 2 × VREFA with either straight binary scale, midscale, or full scale. or twos complement output coding. The conversion time is The AD5590 contains eight low noise, single-supply amplifiers. determined by the ASCLK frequency because it is also used These amplifiers can be used for signal conditioning for the as the master clock to control the conversion. ADCs, DACs, or other independent circuitry, if required. Rev. A | Page 3 of 44 Document Outline Features Applications Functional Block Diagram Revision History General Description Specifications ADC Specifications DAC Specifications DAC AC Characteristics Operational Amplifier Specifications Timing Specifications ADC Timing Characteristics DAC Timing Characteristics Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics DAC ADC Amplifier Terminology Theory of Operation DAC Section Resistor String DAC Internal Reference DAC Output Amplifier ADC Section ADC Converter Operation Analog Input ADC Transfer Function Analog Input Selection Digital Inputs VDRIVE Reference Section Amplifier Section Serial Interface Accessing the DAC Block DAC Input Shift Register Interrupt DAC Internal Reference Register DAC Power-On Reset DAC Power-Down Modes DAC Clear Code Register LDAC Function Accessing the ADC Block ADC Modes of Operation Normal Mode (PM1 = PM0 = 1) Full Shutdown (PM1 = 1, PM0 = 0) AutoShutdown (PM1 = 0, PM0 = 1) Autostandby (PM1 = PM0 = 0) Powering Up the ADC Interfacing to the ADC ADC Control Register ADC Sequencer Operation ADC Shadow Register ADC Power vs. Throughput Rate Outline Dimensions Ordering Guide