Datasheet AD7294 (Analog Devices) - 2
| Manufacturer | Analog Devices |
| Description | 12-Bit Monitor and Control System with Multichannel ADC, DACs, Temperature Sensor, and Current Sense |
| Pages / Page | 47 / 2 — AD7294. Data Sheet. TABLE OF CONTENTS |
| Revision | I |
| File Format / Size | PDF / 1.3 Mb |
| Document Language | English |
AD7294. Data Sheet. TABLE OF CONTENTS
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AD7294 Data Sheet TABLE OF CONTENTS
Features .. 1 TSENSE1, TSENSE2 Result Registers (0x02 and 0x03) .. 29 Applications ... 1 TSENSEINT Result Register (0x04) .. 29 General Description ... 1 DACA, DACB, DACC, DACD, Registers (0x01 to 0x04) ... 30 Revision History ... 3 Alert Status Register A (0x05), Register B (0x06), and Functional Block Diagram .. 4 Register C (0x07) .. 30 Specifications ... 5 Channel Sequence Register (0x08) .. 30 DAC Specifications... 5 Configuration Register (0x09) .. 31 ADC Specifications .. 6 Power-Down Register (0x0A) ... 32 General Specifications ... 8 DATAHIGH/DATALOW Registers: 0x0B, 0x0C (VIN0); 0x0E, 0x0F (VIN1); 0x11, 0x12 (VIN2); 0x14, 0x15 (VIN3) .. 32 Timing Characteristics .. 9 Hysteresis Registers: 0x0D (VIN0), 0x10 (VIN1), 0x13 Absolute Maximum Ratings .. 10 (VIN2), 0x16 (VIN3) ... 32 Thermal Resistance .. 10 TSENSE Offset Registers (0x26 and 0x27) ... 33 ESD Caution .. 10 I2C Interface .. 34 Pin Configurations and Function Descriptions ... 11 General I2C Timing .. 34 Typical Performance Characteristics ... 14 Serial Bus Address Byte ... 35 Terminology .. 19 Interface Protocol ... 35 DAC Terminology .. 19 Modes of Operation ... 39 ADC Terminology .. 19 Command Mode .. 39 Theory of Operation .. 20 Autocycle Mode .. 40 ADC Overview ... 20 Alerts and Limits Theory .. 41 ADC Transfer Functions ... 20 Alert_Flag Bit .. 41 Analog Inputs .. 20 Alert Status Registers ... 41 Current Sensor .. 22 DataHIGH and DataLOW Monitoring Features .. 41 Analog Comparator Loop ... 23 Hysteresis ... 42 Temperature Sensor ... 24 Applications Information .. 43 DAC Operation ... 25 Base Station Power Amplifier Monitor and Control ... 43 ADC and DAC Reference .. 25 Gain Control of Power Amplifier... 44 VDRIVE Feature .. 26 Layout and Configuration ... 45 Register Setting ... 27 Power Supply Bypassing and Grounding .. 45 Address Pointer Register ... 27 Outline Dimensions ... 46 Command Register (0x00) .. 28 Ordering Guide .. 46 Result Register (0x01) .. 28 Rev. I | Page 2 of 47 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS DAC SPECIFICATIONS ADC SPECIFICATIONS GENERAL SPECIFICATIONS TIMING CHARACTERISTICS I2C Serial Interface Timing and Circuit Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY DAC TERMINOLOGY ADC TERMINOLOGY THEORY OF OPERATION ADC OVERVIEW ADC TRANSFER FUNCTIONS ANALOG INPUTS Single-Ended Mode Differential Mode Driving Differential Inputs Using an Op Amp Pair Pseudo Differential Mode CURRENT SENSOR Choosing RSENSE Current Sense Filtering Kelvin Sense Resistor Connection ANALOG COMPARATOR LOOP TEMPERATURE SENSOR Remote Sensing Diode Ideality Factor Base Emitter Voltage Base Resistance hFE Variation Series Resistance Cancellation DAC OPERATION Resistor String Output Amplifier ADC AND DAC REFERENCE VDRIVE FEATURE REGISTER SETTING ADDRESS POINTER REGISTER COMMAND REGISTER (0x00) RESULT REGISTER (0x01) ADC Channel Allocation TSENSE1, TSENSE2 RESULT REGISTERS (0X02 AND 0X03) TSENSEINT RESULT REGISTER (0X04) Temperature Value Format DACA, DACB, DACC, DACD, REGISTERS (0x01 TO 0x04) ALERT STATUS REGISTER A (0x05), REGISTER B (0x06), AND REGISTER C (0x07) CHANNEL SEQUENCE REGISTER (0x08) CONFIGURATION REGISTER (0x09) Sample Delay and Bit Trial Delay POWER-DOWN REGISTER (0x0A) DATAHIGH/DATALOW REGISTERS: 0x0B, 0x0C (VIN0); 0x0E, 0x0F (VIN1); 0x11, 0x12 (VIN2); 0x14, 0x15 (VIN3) HYSTERESIS REGISTERS: 0X0D (VIN0), 0X10 (VIN1), 0X13 (VIN2), 0X16 (VIN3) TSENSE OFFSET REGISTERS (0x26 AND 0x27) I2C INTERFACE GENERAL I2C TIMING SERIAL BUS ADDRESS BYTE INTERFACE PROTOCOL Writing a Single Byte of Data to an 8-Bit Register Writing Two Bytes of Data to a 16-Bit Register Writing to Multiple Registers Reading Data from an 8-Bit Register Reading Two Bytes of Data from a 16-Bit Register MODES OF OPERATION COMMAND MODE AUTOCYCLE MODE ALERTS AND LIMITS THEORY ALERT_FLAG BIT ALERT STATUS REGISTERS DATAHIGH AND DATALOW MONITORING FEATURES HYSTERESIS Using the Limit Registers to Store Minimum/Maximum Conversion Results APPLICATIONS INFORMATION BASE STATION POWER AMPLIFIER MONITOR AND CONTROL GAIN CONTROL OF POWER AMPLIFIER LAYOUT AND CONFIGURATION POWER SUPPLY BYPASSING AND GROUNDING Layout Considerations for External Temperature Sensors OUTLINE DIMENSIONS ORDERING GUIDE
AD7294 Data Sheet TABLE OF CONTENTS
Features .. 1 TSENSE1, TSENSE2 Result Registers (0x02 and 0x03) .. 29 Applications ... 1 TSENSEINT Result Register (0x04) .. 29 General Description ... 1 DACA, DACB, DACC, DACD, Registers (0x01 to 0x04) ... 30 Revision History ... 3 Alert Status Register A (0x05), Register B (0x06), and Functional Block Diagram .. 4 Register C (0x07) .. 30 Specifications ... 5 Channel Sequence Register (0x08) .. 30 DAC Specifications... 5 Configuration Register (0x09) .. 31 ADC Specifications .. 6 Power-Down Register (0x0A) ... 32 General Specifications ... 8 DATAHIGH/DATALOW Registers: 0x0B, 0x0C (VIN0); 0x0E, 0x0F (VIN1); 0x11, 0x12 (VIN2); 0x14, 0x15 (VIN3) .. 32 Timing Characteristics .. 9 Hysteresis Registers: 0x0D (VIN0), 0x10 (VIN1), 0x13 Absolute Maximum Ratings .. 10 (VIN2), 0x16 (VIN3) ... 32 Thermal Resistance .. 10 TSENSE Offset Registers (0x26 and 0x27) ... 33 ESD Caution .. 10 I2C Interface .. 34 Pin Configurations and Function Descriptions ... 11 General I2C Timing .. 34 Typical Performance Characteristics ... 14 Serial Bus Address Byte ... 35 Terminology .. 19 Interface Protocol ... 35 DAC Terminology .. 19 Modes of Operation ... 39 ADC Terminology .. 19 Command Mode .. 39 Theory of Operation .. 20 Autocycle Mode .. 40 ADC Overview ... 20 Alerts and Limits Theory .. 41 ADC Transfer Functions ... 20 Alert_Flag Bit .. 41 Analog Inputs .. 20 Alert Status Registers ... 41 Current Sensor .. 22 DataHIGH and DataLOW Monitoring Features .. 41 Analog Comparator Loop ... 23 Hysteresis ... 42 Temperature Sensor ... 24 Applications Information .. 43 DAC Operation ... 25 Base Station Power Amplifier Monitor and Control ... 43 ADC and DAC Reference .. 25 Gain Control of Power Amplifier... 44 VDRIVE Feature .. 26 Layout and Configuration ... 45 Register Setting ... 27 Power Supply Bypassing and Grounding .. 45 Address Pointer Register ... 27 Outline Dimensions ... 46 Command Register (0x00) .. 28 Ordering Guide .. 46 Result Register (0x01) .. 28 Rev. I | Page 2 of 47 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS DAC SPECIFICATIONS ADC SPECIFICATIONS GENERAL SPECIFICATIONS TIMING CHARACTERISTICS I2C Serial Interface Timing and Circuit Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY DAC TERMINOLOGY ADC TERMINOLOGY THEORY OF OPERATION ADC OVERVIEW ADC TRANSFER FUNCTIONS ANALOG INPUTS Single-Ended Mode Differential Mode Driving Differential Inputs Using an Op Amp Pair Pseudo Differential Mode CURRENT SENSOR Choosing RSENSE Current Sense Filtering Kelvin Sense Resistor Connection ANALOG COMPARATOR LOOP TEMPERATURE SENSOR Remote Sensing Diode Ideality Factor Base Emitter Voltage Base Resistance hFE Variation Series Resistance Cancellation DAC OPERATION Resistor String Output Amplifier ADC AND DAC REFERENCE VDRIVE FEATURE REGISTER SETTING ADDRESS POINTER REGISTER COMMAND REGISTER (0x00) RESULT REGISTER (0x01) ADC Channel Allocation TSENSE1, TSENSE2 RESULT REGISTERS (0X02 AND 0X03) TSENSEINT RESULT REGISTER (0X04) Temperature Value Format DACA, DACB, DACC, DACD, REGISTERS (0x01 TO 0x04) ALERT STATUS REGISTER A (0x05), REGISTER B (0x06), AND REGISTER C (0x07) CHANNEL SEQUENCE REGISTER (0x08) CONFIGURATION REGISTER (0x09) Sample Delay and Bit Trial Delay POWER-DOWN REGISTER (0x0A) DATAHIGH/DATALOW REGISTERS: 0x0B, 0x0C (VIN0); 0x0E, 0x0F (VIN1); 0x11, 0x12 (VIN2); 0x14, 0x15 (VIN3) HYSTERESIS REGISTERS: 0X0D (VIN0), 0X10 (VIN1), 0X13 (VIN2), 0X16 (VIN3) TSENSE OFFSET REGISTERS (0x26 AND 0x27) I2C INTERFACE GENERAL I2C TIMING SERIAL BUS ADDRESS BYTE INTERFACE PROTOCOL Writing a Single Byte of Data to an 8-Bit Register Writing Two Bytes of Data to a 16-Bit Register Writing to Multiple Registers Reading Data from an 8-Bit Register Reading Two Bytes of Data from a 16-Bit Register MODES OF OPERATION COMMAND MODE AUTOCYCLE MODE ALERTS AND LIMITS THEORY ALERT_FLAG BIT ALERT STATUS REGISTERS DATAHIGH AND DATALOW MONITORING FEATURES HYSTERESIS Using the Limit Registers to Store Minimum/Maximum Conversion Results APPLICATIONS INFORMATION BASE STATION POWER AMPLIFIER MONITOR AND CONTROL GAIN CONTROL OF POWER AMPLIFIER LAYOUT AND CONFIGURATION POWER SUPPLY BYPASSING AND GROUNDING Layout Considerations for External Temperature Sensors OUTLINE DIMENSIONS ORDERING GUIDE
