Datasheet ADuCM4050 (Analog Devices) - 24

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ADuCM4050 Data Sheet A IG2 D 1 1 T_ A ND_AN 0_00 0_01 0_02 0_03 1_10 0_10 0_ 1_02 1_03 1_04 1_05 2_01 0_13 0_15 G P P P P P P P P P P P P P P VB 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 VBAT_ANA1 1 48 GND_DIG SYS_HFXTAL_IN 2 47 P1_00 SYS_HFXTAL_OUT 3 46 P0_14 SYS_LFXTAL_IN 4 45 P2_02 SYS_LFXTAL_OUT 5 44 P1_14 VDCDC_CAP1N 6 43 P1_13 VDCDC_CAP1P 7 ADuCM4050 42 P1_12 VBAT_ANA2 8 TOP VIEW 41 P1_11 VDCDC_OUT 9 (Not to Scale) 40 P0_08 VDCDC_CAP2N 10 39 P0_09 VDCDC_CAP2P 11 38 P1_01 VLDO_OUT 12 37 P1_15 VREF_ADC 13 36 P2_00 VBAT_ADC 14 35 P0_12 GND_VREFDAC 15 34 VBAT_DIG1 P2_03 16 33 P2_11 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 ST 2_04 2_05 2_06 2_07 2_08 2_09 2_10 0_05 R 0_04 0_07 0_06 0_09 1_08 1_07 1_06 P P P P P P P P W P P P P P P P H SYS_
015
NOTES 1. EXPOSED PAD. THE EXPOSED PAD MUST BE GROUNDED.
14745- Figure 15. 64-Lead LFCSP Pin Configuration
Table 23. 64-Lead LFCSP Pin Function Descriptions Pin No. Mnemonic Signal Names Description
1 VBAT_ANA1 Not applicable External Supply for Analog Circuits in the MCU. 2 SYS_HFXTAL_IN Not applicable High Frequency Crystal Input. 3 SYS_HFXTAL_OUT Not applicable High Frequency Crystal Output. 4 SYS_LFXTAL_IN Not applicable Low Frequency Crystal Input. 5 SYS_LFXTAL_OUT Not applicable Low Frequency Crystal Output. 6 VDCDC_CAP1N Not applicable Buck Converter Capacitor 1 Negative Terminal. 7 VDCDC_CAP1P Not applicable Buck Converter Capacitor 1 Positive Terminal. 8 VBAT_ANA2 Not applicable External Supply for Analog Circuits in the MCU. 9 VDCDC_OUT Not applicable Buck Converter Output. This pin is only for connecting the decoupling capacitor. Do not connect to external load. 10 VDCDC_CAP2N Not applicable Buck Converter Capacitor 2 Negative Terminal. 11 VDCDC_CAP2P Not applicable Buck Converter Capacitor 2 Positive Terminal. 12 VLDO_OUT Not applicable Low Dropout Regulator Output. This pin is only for connecting the decoupling capacitor. Do not connect to external load. 13 VREF_ADC Not applicable External Reference Voltage for Internal ADC. 14 VBAT_ADC Not applicable External Supply for Internal ADC. 15 GND_VREFADC Not applicable Ground for Internal ADC. 16 P2_03 GPIO35, ADC0_VIN0 GPIO. See the GPIO Multiplexing section for more information. 17 P2_04 GPIO36, ADC0_VIN1 GPIO. See the GPIO Multiplexing section for more information. 18 P2_05 GPIO37, ADC0_VIN2 GPIO. See the GPIO Multiplexing section for more information. 19 P2_06 GPIO38, ADC0_VIN3 GPIO. See the GPIO Multiplexing section for more information. 20 P2_07 GPIO39, ADC0_VIN4, SPI2_CS3 GPIO. See the GPIO Multiplexing section for more information. 21 P2_08 GPIO40, ADC0_VIN5, SPI0_CS2, GPIO. See the GPIO Multiplexing section for more information. RTC1_SS3 22 P2_09 GPIO41, ADC0_VIN6, SPI0_CS3 GPIO. See the GPIO Multiplexing section for more information. 23 P2_10 GPIO42, ADC0_VIN7, SPI2_CS2 GPIO. 24 P0_05 GPIO05, I2C0_SDA GPIO. See the GPIO Multiplexing section for more information. 25 SYS_HWRST Not applicable Hardware Reset Pin. 26 P0_04 GPIO04, I2C0_SCL GPIO. See the GPIO Multiplexing section for more information. 27 P0_07 SWD0_DATA, GPIO07 GPIO. See the GPIO Multiplexing section for more information. Rev. A | Page 24 of 46 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM REVISION HISTORY GENERAL DESCRIPTION PRODUCT HIGHLIGHTS SPECIFICATIONS OPERATING CONDITIONS AND ELECTRICAL CHARACTERISTICS EMBEDDED FLASH SPECIFICATIONS POWER SUPPLY CURRENT SPECIFICATIONS Active Mode Flexi Mode Deep Sleep Modes—VBAT = 1.8 V Deep Sleep Modes—VBAT = 3.0 V Deep Sleep Modes—VBAT = 3.6 V ADC SPECIFICATIONS TEMPERATURE SENSOR SPECIFICATIONS SYSTEM CLOCKS External Crystal Oscillator Specifications On-Chip Resistor-Capacitor (RC) Oscillator Specifications System Clocks and Phase-Locked Loop (PLL) Specifications TIMING SPECIFICATIONS Reset Timing Serial Ports Timing SPI Timing I2C Specifications General-Purpose Port Timing RTC1 (FLEX_RTC) Specifications Timer Pulse-Width Modulation (PWM) Output Cycle Timing ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION ARM CORTEX-M4F PROCESSOR ARM Cortex-M4F Subsystem Code Region SRAM Region System Region MEMORY ARCHITECTURE SRAM Region MMRs (Peripheral Control and Status) Flash Memory Cache Controller SYSTEM INTEGRATION FEATURES Reset Booting Power Management and Modes Active Mode Flexi Mode Hibernate Mode Shutdown Mode Shutdown Mode—Fast Wake-Up Power Management and Control Security Features Cryptographic Accelerator True Random Number Generator (TRNG) Reliability and Robustness Features ECC Enabled Flash Memory Multiparity Bit Protected SRAM Software Watchdog CRC Accelerator Programmable GPIOs Timers General-Purpose Timers Watchdog Timer (WDT) RGB Timer ADC Subsystem Clocking Clock Fail Detection Real-Time Clock (RTC) Beeper Driver Debug Capability ON-CHIP PERIPHERAL FEATURES Serial Ports (SPORT) SPI Ports UART Ports I2C DEVELOPMENT SUPPORT Documentation Hardware Software REFERENCE DESIGNS SECURITY FEATURES DISCLAIMER MCU TEST CONDITIONS DRIVER TYPES EEMBC ULPMARK™-CP SCORE GPIO MULTIPLEXING APPLICATIONS INFORMATION SILICON ANOMALY ADuCM4050 FUNCTIONALITY ISSUES FUNCTIONALITY ISSUES SECTION 1. ADuCM4050 FUNCTIONALITY ISSUES OUTLINE DIMENSIONS ORDERING GUIDE