Datasheet LTM4686, LTM4686-1 (Analog Devices) - 79
| Manufacturer | Analog Devices |
| Description | Ultrathin Dual 10A or Single 20A μModule Regulator with Digital Power System Management |
| Pages / Page | 132 / 79 — APPENDIX B. PMBUS SERIAL DIGITAL INTERFACE. Figure 36. Timing Diagram |
| Revision | B |
| File Format / Size | PDF / 3.3 Mb |
| Document Language | English |
APPENDIX B. PMBUS SERIAL DIGITAL INTERFACE. Figure 36. Timing Diagram
Model Line for this Datasheet
Text Version of Document
link to page 79 link to page 80 link to page 82 link to page 80 LTM4686/LTM4686-1
APPENDIX B PMBUS SERIAL DIGITAL INTERFACE
supports 255 bytes of returned data. For this reason, the The LTM4686 communicates with a host (master) using the PMBus timeout may be extended when reading the fault log. standard PMBus serial bus interface. The Timing Diagram, Figure 37 is a key to the protocol diagrams in this section. Figure 36, shows the timing relationship of the signals on PEC is optional. the bus. The two bus lines, SDA and SCL, must be high A value shown below a field in the following figures is a when the bus is not in use. External pull-up resistors or mandatory value for that field. current sources are required on these lines. The data formats implemented by PMBus are: The LTM4686 is a slave device. The master can com- municate with the LTM4686 using the following formats: n Master transmitter transmits to slave receiver. The transfer direction in this case is not changed. n Master transmitter, slave receiver n Master reads slave immediately after the first byte. At n Master receiver, slave transmitter the moment of the first acknowledgment (provided by The following PMBus protocols are supported: the slave receiver) the master transmitter becomes a master receiver and the slave receiver becomes a slave n Write Byte, Write Word, Send Byte, Block Write transmitter. n Read Byte, Read Word, Block Read n Combined format. During a change of direction within n Block Write -- Block Read Process Call a transfer, the master repeats both a start condition and the slave address but with the R/W bit reversed. n Alert Response Address In this case, the master receiver terminates the transfer Figure 38 to Figure 54 illustrate the aforementioned PMBus by generating a NACK on the last byte of the transfer protocols. All transactions support PEC (parity error check) and a STOP condition. and GCP (group command protocol). The Block Read SDA tr tSU(DAT) t t t HD(SDA) tSP r tf LOW t t f BUF SCL tHD(STA) tSU(STA) tSU(STO) tHD(DAT) tHIGH 46861 F36 START REPEATED START STOP START CONDITION CONDITION CONDITION CONDITION
Figure 36. Timing Diagram
Rev. B For more information www.analog.com 79 Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Order Information Pin Configuration Electrical Characteristics Typical Performance Characteristics Pin Functions Simplified Block Diagram Decoupling Requirements Functional Diagram Test Circuits Operation Power Module Introduction Power Module Configurability and Readback Data Time-Averaged and Peak Readback Data Power Module Overview EEPROM Serial Interface Device Addressing Fault Detection and Handling Responses to VOUT and IOUT Faults Responses to Timing Faults Responses to SVIN OV Faults Responses to OT/UT Faults Responses to External Faults Fault Logging Bus Timeout Protection PMBus Command Summary PMBus Commands Applications Information VIN to VOUT Step-Down Ratios Input Capacitors Output Capacitors Light Load Current Operation Switching Frequency and Phase Minimum On-Time Considerations Variable Delay Time, Soft-Start and Output Voltage Ramping Digital Servo Mode Soft Off (Sequenced Off) Undervoltage Lockout Fault Detection and Handling Open-Drain Pins Phase-Locked Loop and Frequency Synchronization RCONFIG Pin-Straps (External Resistor Configuration Pins) Voltage Selection Connecting the USB to the I2C/SMBus/PMBus Controller to the LTM4686 In System LTpowerPlay: An Interactive GUI for Digital Power System Management PMBus Communication and Command Processing Thermal Considerations and Output Current Derating EMI Performance Safety Considerations Layout Checklist/Example Typical Applications Appendix A Similarity Between PMBus, SMBus and I2C 2-Wire Interface Appendix B PMBus Serial Digital Interface Appendix C: PMBus Command Details Addressing and Write Protect General Configuration Registers On/Off/Margin PWM Config Voltage Current Temperature Timing Fault Response Fault Sharing Scratchpad Identification Fault Warning and Status Telemetry NVM (EEPROM) Memory Commands Package Description Package Photographs Package Description Revision History Typical Application Design Resources Related Parts
APPENDIX B PMBUS SERIAL DIGITAL INTERFACE
supports 255 bytes of returned data. For this reason, the The LTM4686 communicates with a host (master) using the PMBus timeout may be extended when reading the fault log. standard PMBus serial bus interface. The Timing Diagram, Figure 37 is a key to the protocol diagrams in this section. Figure 36, shows the timing relationship of the signals on PEC is optional. the bus. The two bus lines, SDA and SCL, must be high A value shown below a field in the following figures is a when the bus is not in use. External pull-up resistors or mandatory value for that field. current sources are required on these lines. The data formats implemented by PMBus are: The LTM4686 is a slave device. The master can com- municate with the LTM4686 using the following formats: n Master transmitter transmits to slave receiver. The transfer direction in this case is not changed. n Master transmitter, slave receiver n Master reads slave immediately after the first byte. At n Master receiver, slave transmitter the moment of the first acknowledgment (provided by The following PMBus protocols are supported: the slave receiver) the master transmitter becomes a master receiver and the slave receiver becomes a slave n Write Byte, Write Word, Send Byte, Block Write transmitter. n Read Byte, Read Word, Block Read n Combined format. During a change of direction within n Block Write -- Block Read Process Call a transfer, the master repeats both a start condition and the slave address but with the R/W bit reversed. n Alert Response Address In this case, the master receiver terminates the transfer Figure 38 to Figure 54 illustrate the aforementioned PMBus by generating a NACK on the last byte of the transfer protocols. All transactions support PEC (parity error check) and a STOP condition. and GCP (group command protocol). The Block Read SDA tr tSU(DAT) t t t HD(SDA) tSP r tf LOW t t f BUF SCL tHD(STA) tSU(STA) tSU(STO) tHD(DAT) tHIGH 46861 F36 START REPEATED START STOP START CONDITION CONDITION CONDITION CONDITION
Figure 36. Timing Diagram
Rev. B For more information www.analog.com 79 Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Order Information Pin Configuration Electrical Characteristics Typical Performance Characteristics Pin Functions Simplified Block Diagram Decoupling Requirements Functional Diagram Test Circuits Operation Power Module Introduction Power Module Configurability and Readback Data Time-Averaged and Peak Readback Data Power Module Overview EEPROM Serial Interface Device Addressing Fault Detection and Handling Responses to VOUT and IOUT Faults Responses to Timing Faults Responses to SVIN OV Faults Responses to OT/UT Faults Responses to External Faults Fault Logging Bus Timeout Protection PMBus Command Summary PMBus Commands Applications Information VIN to VOUT Step-Down Ratios Input Capacitors Output Capacitors Light Load Current Operation Switching Frequency and Phase Minimum On-Time Considerations Variable Delay Time, Soft-Start and Output Voltage Ramping Digital Servo Mode Soft Off (Sequenced Off) Undervoltage Lockout Fault Detection and Handling Open-Drain Pins Phase-Locked Loop and Frequency Synchronization RCONFIG Pin-Straps (External Resistor Configuration Pins) Voltage Selection Connecting the USB to the I2C/SMBus/PMBus Controller to the LTM4686 In System LTpowerPlay: An Interactive GUI for Digital Power System Management PMBus Communication and Command Processing Thermal Considerations and Output Current Derating EMI Performance Safety Considerations Layout Checklist/Example Typical Applications Appendix A Similarity Between PMBus, SMBus and I2C 2-Wire Interface Appendix B PMBus Serial Digital Interface Appendix C: PMBus Command Details Addressing and Write Protect General Configuration Registers On/Off/Margin PWM Config Voltage Current Temperature Timing Fault Response Fault Sharing Scratchpad Identification Fault Warning and Status Telemetry NVM (EEPROM) Memory Commands Package Description Package Photographs Package Description Revision History Typical Application Design Resources Related Parts
