Datasheet HIP2210, HIP2211 (Renesas) - 3

HIP2210, HIP2211 1. Overview
1. Overview 1.1 Block Diagrams VDD HB VDD HB Gate UVLO HO UVLO Drive VREF 500k HS 200k Level - Delay Shift PWM + - 200k + Gat e Delay LO Drive 100k EN VSS 100k Prog Dead Time RDT Figure 3. HIP2210 Block Diagram VDD HB HB Gat e HO VDD UVLO Drive UVLO 500k HS HI Level Shift 100k Gate Drive LO LI 100k 100k VSS Figure 4. HIP2211 Block Diagram
FN9347 Rev.1.01 Page 3 of 27 Jun.23.20 Document Outline Related Literature Features Applications Contents 1. Overview 1.1 Block Diagrams 1.2 Ordering Information 1.3 Pin Configurations 1.4 Pin Descriptions 2. Specifications 2.1 Absolute Maximum Ratings 2.2 Thermal Information 2.3 Recommended Operating Conditions 2.4 Electrical Specifications 2.5 Switching Specifications 2.6 Timing Diagrams 3. Typical Performance Curves 4. Functional Description 4.1 Gate Drive for NMOS Half-Bridge 4.2 Functional Overview 5. Applications Information 5.1 HI/LI Input Control (HIP2211 Only) 5.2 PWM Input Control (HIP2210 Only) 5.3 VREF Input (HIP2210 Only) 5.4 EN Pin (HIP2210 Only) 5.5 Power Sequencing HIP2210 5.6 Selecting the Boot Capacitor Value 5.7 VDD Decoupling Capacitor 5.8 RDT and Dead Time Delay (HIP2210 Only) 5.9 HO and LO Outputs 5.10 Power Dissipation 5.10.1 Gate Power (for the HO and LO Outputs) 5.10.2 Boot Diode Dissipation 5.10.3 Dynamic Operating Current 5.10.4 Total Power Dissipation 5.10.5 Junction Operating Temperature 6. PCB Layout Guidelines 6.1 PCB Layout and EPAD Recommendation 7. Revision History 8. Package Outline Drawings