Datasheet ADRV9002 (Analog Devices)

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Dual Narrow/Wideband RF Transceiver Preliminary Technical Data ADRV9002 FEATURES
The transceiver consists of direct conversion signal paths with state of the art noise figure and linearity. Each complete
2 × 2 highly integrated transceiver
receiver and transmitter subsystem includes dc offset
Frequency range of 30 MHz to 6000 MHz Transmitter and receiver bandwidth up to 40 MHz
correction, quadrature error correction, and programmable
Fully integrated, fractional-N, RF synthesizers
digital filters, which eliminate the need for these functions in
LVDS and CSSI
the digital baseband. In addition, several auxiliary functions
Low power monitor and sleep modes
such as auxiliary analog-to-digital converters (ADCs), auxiliary
Multichip synchronization capabilities
digital-to-analog converters (DACs), and general-purpose
FFH
input/outputs (GPIOs) are integrated to provide additional
Dynamic profile switching for dynamic data rates and
monitoring and control capability.
sample rates
The fully integrated phase-locked loops (PLLs) provide high
Fully integrated DPD for narrowband and wideband
performance, low power, fractional-N frequency synthesis for
waveforms
the transmitter, receiver, and clock sections. Careful design and
Fully programmable via a 4-wire SPI
layout techniques provide the isolation required in high
12 mm × 12 mm, 196-ball CSP_BGA
performance personal radio applications.
APPLICATIONS
All voltage controlled oscillator (VCO) and loop filter
Mission critical communications
components are integrated to minimize the external
Very high frequency (VHF), ultrahigh frequency (UHF), and
component count. The local oscillators (LOs) have flexible
cellular to 6 GHz
configuration options and include fast lock modes.
Time division duplexing (TDD) and frequency division
The transceiver includes low power sleep and monitor modes
duplexing (FDD) applications
to save power and extend the battery life of portable devices while monitoring communication.
GENERAL DESCRIPTION
The fully integrated, low power digital predistortion (DPD) is The ADRV9002 is a highly integrated, RF transceiver that has optimized for both narrowband and wideband signals and dual-channel transmitters, dual-channel receivers, integrated enables linearization of high efficiency power amplifiers. synthesizers, and digital signal processing functions. The ADRV9002 core can be powered directly from 1.0 V, 1.3 V, The IC delivers a versatile combination of high performance and 1.8 V regulators and is controlled via a standard 4-wire and low power consumption required by battery powered radio serial port. Other voltage supplies are used to provide proper equipment and can operate in both FDD and TDD modes. The digital interface levels and to optimize receiver, transmitter, and ADRV9002 operates from 30 MHz to 6000 MHz and covers the auxiliary converter performance. UHF, VHF, licensed and unlicensed cellular bands, and industrial, scientific, and medical (ISM) bands. The IC can High data rate and low data rate interfaces are supported using support both narrowband and wideband standards up to configurable complementary metal-oxide semiconductors 40 MHz bandwidth on both receive and transmit. (CMOS) or low voltage differential signaling (LVDS) serial synchronous interface (SSI) choice. The ADRV9002 is packaged in a 12 mm × 12 mm, 196-ball chip scale package ball grid array (CSP_BGA).
Rev. PrA Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. No license is granted by implication or otherwise under any patent or patent rights of Analog Tel: 781.329.4700 ©2020 Analog Devices, Inc. All rights reserved. Devices. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com
Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION TABLE OF CONTENTS FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS TRANSMITTER SPECIFICATIONS RECEIVER SPECIFICATIONS INTERNAL LO, EXTERNAL LO, AND DEVICE CLOCK DIGITAL INTERFACES AND AUXILIARY CONVERTERS POWER SUPPLY SPECIFICATIONS CURRENT CONSUMPTION ESTIMATES (TYPICAL VALUES) Sleep Mode (Typical Values) TDD Operation (Typical Values) FDD Operation (Typical Values) TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS REFLOW PROFILE THERMAL RESISTANCE ELECTROSTATIC DISCHARGE (ESD) RATINGS ESD Ratings for ADRV2009 ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS 30 MHZ BAND 470 MHZ BAND 900 MHZ BAND 2400 MHZ BAND 3500 MHZ BAND 5800 MHZ BAND PHASE NOISE THEORY OF OPERATION TRANSMITTER RECEIVER Monitor Mode DPD Receiver as an Observation Receiver CLOCK INPUT SYNTHESIZERS RF PLL Baseband PLL (PLL) SPI INTERFACE GPIO PINS Digital GPIO Inputs/Outputs (DGPIO) Analog GPIO Inputs/Outputs (AGPIO) AUXILLARY CONVERTERS Auxiliary ADC Inputs (AUXADC_x) Auxiliary DACs Outputs (AUXDAC_x) JTAG BOUNDARY SCAN APPLICATIONS INFORMATION POWER SUPPLY SEQUENCE DIGITAL DATA INTERFACE CSSI CSSI Receive CSSI Transmit LSSI OUTLINE DIMENSIONS