Datasheet AD9371 (Analog Devices) - 6

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AD9371 Data Sheet Parameter Symbol Min Typ Max Unit Test Conditions/Comments
Input Third-Order Intercept Point IIP3 Maximum ORx gain, IM3 1 MHz offset from LO 700 MHz LO 22 dBm 2600 MHz LO 22 dBm 3500 MHz LO 18 dBm 5500 MHz LO 18 dBm Input Second-Order Intercept IIP2 Maximum ORx gain, IM2 Point 1 MHz offset from LO 700 MHz LO 65 dBm 2600 MHz LO 65 dBm 3500 MHz LO 65 dBm 5500 MHz LO 60 dBm Image Rejection After online tone calibration 700 MHz LO 65 dB 2600 MHz LO 65 dB 3500 MHz LO 65 dB 5500 MHz LO 65 dB Input Impedance 200 Ω Differential Tx1 to ORx1 Signal and Tx2 to ORx2 Signal Isolation 700 MHz LO 70 dB 2600 MHz LO 70 dB 3500 MHz LO 70 dB 5500 MHz LO 70 dB Tx1 to ORx2 Signal and Tx2 to ORx1 Signal Isolation 700 MHz LO 70 dB 2600 MHz LO 70 dB 3500 MHz LO 70 dB 5500 MHz LO 70 dB SNIFFER RECEIVER (SnRx) Center Frequency 300 4000 MHz Gain Range 0 52 dB Analog Gain Step 1 dB BW Ripple ±0.5 dB 20 MHz RF BW, compensated by programmable FIR filter Rx Bandwidth 20 MHz Rx Alias Band Rejection 60 dB Due to digital filters Maximum Recommended Input −26 dBm Input is a CW7 signal at 0 dB Power8 attenuation setting Noise Figure NF Maximum gain at SnRx port, matching losses de-embedded, gain control limited to the first 20 steps 700 MHz LO 5 dB 2600 MHz LO 5 dB 3500 MHz LO 7 dB Input Third-Order Intercept Point IIP3 Maximum gain, IM3 1 MHz offset from LO, gain control limited to the first 20 steps 700 MHz LO 1 dBm 2600 MHz LO 1 dBm 3500 MHz LO 1 dBm Rev. B | Page 6 of 57 Document Outline Features Applications General Description Functional Block Diagram Revision History Specifications Current and Power Consumption Specifications Timing Specifications Timing Diagrams Absolute Maximum Ratings Reflow Profile Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics 700 MHz Band 2.6 GHz Band 3.5 GHz Band 5.5 GHz Band Theory of Operation Transmitter (Tx) Receiver (Rx) Observation Receiver (ORx) Sniffer Receiver (SnRx) Clock Input Synthesizers RF PLL Clock PLL External LO Inputs Serial Peripheral Interface (SPI) Interface GPIO_x AND GPIO_3P3_x Pins Auxiliary Converters Auxiliary ADC Inputs (AUXADC_x) Auxiliary DACs (AUXDAC_x) JESD204B Data Interface Power Supply Sequence JTAG Boundary Scan Outline Dimensions Ordering Guide