Datasheet AD9371 (Analog Devices) - 8
| Manufacturer | Analog Devices |
| Description | Integrated, Dual RF Transceiver with Observation Path |
| Pages / Page | 57 / 8 — AD9371. Data Sheet. Parameter Symbol. Min. Typ. Max. Unit. Test. … |
| Revision | B |
| File Format / Size | PDF / 879 Kb |
| Document Language | English |
AD9371. Data Sheet. Parameter Symbol. Min. Typ. Max. Unit. Test. Conditions/Comments
Model Line for this Datasheet
Text Version of Document
AD9371 Data Sheet Parameter Symbol Min Typ Max Unit Test Conditions/Comments
REFERENCE CLOCK (DEV_CLK_IN SIGNAL) Frequency Range 10 320 MHz Signal Level 0.3 2.0 V p-p AC-coupled, common-mode voltage (VCM) = 618 mV; for best spurious performance, use a <1 V p-p input clock AUXILIARY CONVERTERS ADC ADC Resolution 12 Bits Input Voltage Minimum 0.25 V Maximum 3.05 V DAC DAC Resolution 10 Bits Includes four offset levels Output Voltage Minimum 0.5 V Reference voltage (VREF) = 1 V Maximum 3.0 V VREF = 2.5 V Drive Capability 10 mA DIGITAL SPECIFICATIONS (CMOS), GPIO_x, RX1_ENABLE, RX2_ENABLE, TX1_ENABLE, TX2 ENABLE, SYNCINBx+, SYNCOUTB0+, GP_INTERRUPT, SDIO, SDO, SCLK, CSB, RESET Logic Inputs Input Voltage High Level VDD_IF × VDD_IF V 0.8 Low Level 0 VDD_IF × V 0.2 Input Current High Level −10 +10 μA Low Level −10 +10 μA Logic Outputs Output Voltage High Level VDD_IF × V 0.8 Low Level VDD_IF × V 0.2 Drive Capability 3 mA DIGITAL SPECIFICATIONS (LVDS), SYSREF_INx, SYNCOUTB0±, SYNCINBx PAIRS Logic Inputs Input Voltage Range 825 1675 mV Each differential input in the pair Input Differential Voltage −100 +100 mV Threshold Receiver Differential Input 100 Ω Internal termination enabled Impedance Rev. B | Page 8 of 57 Document Outline Features Applications General Description Functional Block Diagram Revision History Specifications Current and Power Consumption Specifications Timing Specifications Timing Diagrams Absolute Maximum Ratings Reflow Profile Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics 700 MHz Band 2.6 GHz Band 3.5 GHz Band 5.5 GHz Band Theory of Operation Transmitter (Tx) Receiver (Rx) Observation Receiver (ORx) Sniffer Receiver (SnRx) Clock Input Synthesizers RF PLL Clock PLL External LO Inputs Serial Peripheral Interface (SPI) Interface GPIO_x AND GPIO_3P3_x Pins Auxiliary Converters Auxiliary ADC Inputs (AUXADC_x) Auxiliary DACs (AUXDAC_x) JESD204B Data Interface Power Supply Sequence JTAG Boundary Scan Outline Dimensions Ordering Guide
REFERENCE CLOCK (DEV_CLK_IN SIGNAL) Frequency Range 10 320 MHz Signal Level 0.3 2.0 V p-p AC-coupled, common-mode voltage (VCM) = 618 mV; for best spurious performance, use a <1 V p-p input clock AUXILIARY CONVERTERS ADC ADC Resolution 12 Bits Input Voltage Minimum 0.25 V Maximum 3.05 V DAC DAC Resolution 10 Bits Includes four offset levels Output Voltage Minimum 0.5 V Reference voltage (VREF) = 1 V Maximum 3.0 V VREF = 2.5 V Drive Capability 10 mA DIGITAL SPECIFICATIONS (CMOS), GPIO_x, RX1_ENABLE, RX2_ENABLE, TX1_ENABLE, TX2 ENABLE, SYNCINBx+, SYNCOUTB0+, GP_INTERRUPT, SDIO, SDO, SCLK, CSB, RESET Logic Inputs Input Voltage High Level VDD_IF × VDD_IF V 0.8 Low Level 0 VDD_IF × V 0.2 Input Current High Level −10 +10 μA Low Level −10 +10 μA Logic Outputs Output Voltage High Level VDD_IF × V 0.8 Low Level VDD_IF × V 0.2 Drive Capability 3 mA DIGITAL SPECIFICATIONS (LVDS), SYSREF_INx, SYNCOUTB0±, SYNCINBx PAIRS Logic Inputs Input Voltage Range 825 1675 mV Each differential input in the pair Input Differential Voltage −100 +100 mV Threshold Receiver Differential Input 100 Ω Internal termination enabled Impedance Rev. B | Page 8 of 57 Document Outline Features Applications General Description Functional Block Diagram Revision History Specifications Current and Power Consumption Specifications Timing Specifications Timing Diagrams Absolute Maximum Ratings Reflow Profile Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics 700 MHz Band 2.6 GHz Band 3.5 GHz Band 5.5 GHz Band Theory of Operation Transmitter (Tx) Receiver (Rx) Observation Receiver (ORx) Sniffer Receiver (SnRx) Clock Input Synthesizers RF PLL Clock PLL External LO Inputs Serial Peripheral Interface (SPI) Interface GPIO_x AND GPIO_3P3_x Pins Auxiliary Converters Auxiliary ADC Inputs (AUXADC_x) Auxiliary DACs (AUXDAC_x) JESD204B Data Interface Power Supply Sequence JTAG Boundary Scan Outline Dimensions Ordering Guide
