Datasheet AD9364 (Analog Devices) - 5

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Data Sheet AD9364 Parameter1 Symbol Min Typ Max Unit Test Conditions/Comments
Output Voltage Minimum 0.5 V Maximum VDD_GPO − 0.3 V Output Current 10 mA DIGITAL SPECIFICATIONS (CMOS) Logic Inputs Input Voltage High VDD_INTERFACE × 0.8 VDD_INTERFACE V Low 0 VDD_INTERFACE × 0.2 V Input Current High −10 +10 μA Low −10 +10 μA Logic Outputs Output Voltage High VDD_INTERFACE × 0.8 V Low VDD_INTERFACE × 0.2 V DIGITAL SPECIFICATIONS (LVDS) Logic Inputs Input Voltage Range 825 1575 mV Each differential input in the pair Input Differential Voltage −100 +100 mV Threshold Receiver Differential Input 100 Ω Impedance Logic Outputs Output Voltage High 1375 mV Low 1025 mV Output Differential Voltage 150 mV Programmable in 75 mV steps Output Offset Voltage 1200 mV GENERAL-PURPOSE OUTPUTS Output Voltage High VDD_GPO × 0.8 V Low VDD_GPO × 0.2 V Output Current 10 mA SPI TIMING VDD_INTERFACE = 1.8 V SPI_CLK Period tCP 20 ns Pulse Width tMP 9 ns SPI_ENB Setup to First SPI_CLK tSC 1 ns Rising Edge Last SPI_CLK Fal ing Edge to tHC 0 ns SPI_ENB Hold SPI_DI Data Input Setup to tS 2 ns SPI_CLK Data Input Hold to SPI_CLK tH 1 ns SPI_CLK Rising Edge to Output Data Delay 4-Wire Mode tCO 3 8 ns 3-Wire Mode tCO 3 8 ns Bus Turnaround Time, Read tHZM tH tCO (max) ns After baseband processor (BBP) drives the last address bit Bus Turnaround Time, Read tHZS 0 tCO (max) ns After the AD9364 drives the last data bit Rev. C | Page 5 of 32 Document Outline Features Applications Functional Block Diagram General Description Table of Contents Revision History Specifications Current Consumption—VDD_Interface Current Consumption—VDDD1P3_DIG and VDDAx (Combination of All 1.3 V Supplies) Absolute Maximum Ratings Reflow Profile Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics 800 MHz Frequency Band 2.4 GHz Frequency Band 5.5 GHz Frequency Band Theory of Operation General Receiver Transmitter Clock Input Options Synthesizers RF PLLs BB PLL Digital Data Interface DATA_CLK Signal FB_CLK Signal RX_FRAME Signal Enable State Machine SPI Control Mode Pin Control Mode SPI Interface Control Pins Control Outputs (CTRL_OUT7 to CTRL_OUT0) Control Inputs (CTRL_IN3 to CTRL_IN0) GPO Pins (GPO_3 to GPO_0) Auxiliary Converters AUXADC AUXDAC1 and AUXDAC2 Powering the AD9364 Packaging and Ordering Information Outline Dimensions Ordering Guide