Datasheet AD9364 (Analog Devices) - 7

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Data Sheet AD9364 Parameter1 Symbol Min Typ Max Unit Test Conditions/Comments
Bus Turnaround Time Before Rx tRPRE 2 × tCP ns After Rx tRPST 2 × tCP ns Capacitive Load 3 pF Capacitive Input 3 pF SUPPLY CHARACTERISTICS 1.3 V Main Supply Voltage 1.267 1.3 1.33 V VDD_INTERFACE Supply Nominal Settings CMOS 1.14 2.625 V LVDS 1.71 2.625 V VDD_INTERFACE Tolerance −5 +5 % Tolerance is applicable to any voltage setting VDD_GPO Supply Nominal 1.3 3.3 V When unused, must be set Setting to 1.3 V VDD_GPO Tolerance −5 +5 % Tolerance is applicable to any voltage setting Current Consumption VDDx, Sleep Mode 180 μA Sum of all input currents VDD_GPO 50 μA No load 1 When referencing a single function of a multifunction pin in the parameters, only the portion of the pin name that is relevant to the specification is listed. For full pin names of multifunction pins, refer to the Pin Configuration and Function Descriptions section.
CURRENT CONSUMPTION—VDD_INTERFACE Table 2. VDD_INTERFACE = 1.2 V Parameter Min Typ Max Unit Test Conditions/Comments
SLEEP MODE 45 μA Power applied, device disabled RX AND TX, DOUBLE DATA RATE (DDR) LTE 10 MHz Single Port 2.9 mA 30.72 MHz data clock, CMOS Dual Port 2.7 mA 15.36 MHz data clock, CMOS LTE 20 MHz Dual Port 5.2 mA 30.72 MHz data clock, CMOS
Table 3. VDD_INTERFACE = 1.8 V Parameter Min Typ Max Unit Test Conditions/Comments
SLEEP MODE 84 μA Power applied, device disabled RX AND TX, DDR LTE 10 MHz Single Port 4.5 mA 30.72 MHz data clock, CMOS Dual Port 4.1 mA 15.36 MHz data clock, CMOS LTE 20 MHz Dual Port 8.0 mA 30.72 MHz data clock, CMOS
Table 4. VDD_INTERFACE = 2.5 V Parameter Min Typ Max Unit Test Conditions/Comments
SLEEP MODE 150 μA Power applied, device disabled RX AND TX, DDR LTE 10 MHz Single Port 6.5 mA 30.72 MHz data clock, CMOS Dual Port 6.0 mA 15.36 MHz data clock, CMOS LTE 20 MHz Dual Port 11.5 mA 30.72 MHz data clock, CMOS Rev. C | Page 7 of 32 Document Outline Features Applications Functional Block Diagram General Description Table of Contents Revision History Specifications Current Consumption—VDD_Interface Current Consumption—VDDD1P3_DIG and VDDAx (Combination of All 1.3 V Supplies) Absolute Maximum Ratings Reflow Profile Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics 800 MHz Frequency Band 2.4 GHz Frequency Band 5.5 GHz Frequency Band Theory of Operation General Receiver Transmitter Clock Input Options Synthesizers RF PLLs BB PLL Digital Data Interface DATA_CLK Signal FB_CLK Signal RX_FRAME Signal Enable State Machine SPI Control Mode Pin Control Mode SPI Interface Control Pins Control Outputs (CTRL_OUT7 to CTRL_OUT0) Control Inputs (CTRL_IN3 to CTRL_IN0) GPO Pins (GPO_3 to GPO_0) Auxiliary Converters AUXADC AUXDAC1 and AUXDAC2 Powering the AD9364 Packaging and Ordering Information Outline Dimensions Ordering Guide