Datasheet LTM4663 (Analog Devices) - 6

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PIN FUNCTIONS GNDP (A1):
Power Ground Pin for PWM Switching Mode
GNDA (D1):
Signal Ground Pin for the Internal Control Regulator. Connect to GNDL with large PCB copper area. Circuits. Return ground path of all analog circuitry. Tie a
SW (A2, B2):
Switching node of the PWM Switching single connection to the GNDP/GNDL in the application. Mode Regulator that is used for testing purposes. R-C See layout guidelines in Figure 17. snubber network can be applied to reduce or eliminate
EN/SY (D2):
Enable and External Synchronization Input switch node ringing, or otherwise leave floating. of the TEC Driver. Set this pin logic high to enable the
PV
device. An external synchronization clock input can be
IN (A3, B3):
Power Input Pins for Both PWM Switching Mode Regulator and Linear Power Stage. Apply input applied to this pin. voltage between these pins and GNDP/GNDL pins.
PAMPOUT (D3):
Output of the Compensation Amplifier. Recommend placing input decoupling capacitance directly
PAMPN (D4):
Inverting Input of the Compensation between PVIN pins and GNDP pins. Amplifier.
VLDR (A4, B4):
Linear Power Output Pin. Apply the TEC
NC (D5):
Pin used for testing purposes. Leave floating. device between VPWM pin and VLDR pin. Do not connect.
GNDL (A5, B5):
Power Ground Pin for Linear Power
V
Stage. Connect to GNDP with large PCB copper area.
REF (E1):
2.5V Internal Reference Output Voltage. This pin is internal decoupled with 0.1µF capacitor. No addi-
VPWM (B1):
PWM Switching Mode Regulator Power tional decoupling is required. Output Pin. Apply the TEC device between VPWM pin and
SV
V
IN (E2):
Signal VIN. Filtered Input Voltage to the LDR pin. Recommend placing output decoupling capac- Internal Control Circuits. Connect to PV itance directly between V IN directly in most PWM pins and GNDP pins. applications.
SFB (C1):
PWM Switching Mode Regulator Voltage
I
Feedback Pin. Connect this pin close to the TEC device.
LIM (E3):
Current Limit Set Pin. An external resistor divider RCT/RCB between VREF and GNDA sets the TEC driver
VTEC (C2):
Voltage Monitor Pin for the TEC device. cooling and heating current limits. See the Applications
I
Information section for details.
TEC (C3):
Current Monitor Pin for the TEC device.
T VLIM/SD (E4):
Voltage Limit Set Pin. An external resistor
FB (C4):
Temperature Feedback Pin. Connect this pin to the thermistor input. This is connected to the inverting between this pin and GNDA sets the TEC driver cooling and input of the thermistor temperature error amplifier. See heating voltage limits. See the Applications Information the Applications Information section for details. section for details.
TAMPOUT (C5):
Output of the Thermistor Temperature
TSET (E5):
Temperature Set Pin for the TEC Driver. This pin Error Amplifier. is the non-inverting input of the compensation amplifier. The TSET voltage controls the target temperature of the thermistor, by either sinking or sourcing current from the TEC device. Rev. 0 6 For more information www.analog.com Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Order Information Electrical Characteristics Pin Configuration Typical Performance Characteristics Pin Functions Block Diagram Decoupling Requirements Operation Applications Information Typical Applications Package Description Package Photo Package Description Design Resources Related Parts