Datasheet LTM4663 (Analog Devices) - 9

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APPLICATIONS INFORMATION
TEMPERATURE ERROR PID COMPENSATION AMPLIFIER AMPLIFIER LINEAR V A LDR V = RFB/(RTH + RX) – RFB /R +1 AV = Z2/Z1 POWER STAGE CHOPPER 1 CHOPPER 2 + VREF/2 + + CONTROL TEC – – – PWM SWITCHING TAMPOUT T MODE REGULATOR VREF TFB SET PAMPN PAMPOUT VPWM LTM4663 F02 R VTSET RFB R Z X 1 Z2 RTH
Figure 2. LTM4663 Control Signal Flow Chart
below 0.07V, the controller goes into an ultralow current applied to the EN/SY input pin. The clock high level must state. The current drawn in shutdown mode is 480µA be above 2.1V and the clock low level below 0.8V. typically. Most of the current is consumed by the VREF circuit block, which is always on even when the device is
SOFT-START
disabled or shut down. The device can also be enabled when an external synchronization clock signal is applied The LTM4663 has an internal soft-start circuit that gen- to the EN/SY pin, and the voltage at V erates a ramp with a typical 150ms profile to minimize LIM/SD input is above 0.07V. Table 1 shows the combinations of the two input inrush current during power-up. The settling time and the signals that are required to enable the LTM4663. final voltage across the TEC depends on the TEC voltage required by the control voltage of voltage loop. The higher
Table 1. Enable Pin Combinations
the TEC voltage is, the longer it requires to reach the final
EN/SY PIN VLIM/SD PIN STATUS
output voltage. >2.1V >0.07V Enable When the LTM4663 is first powered up, the linear side Clock >0.07V Enable discharges the output of any prebias voltage. As soon <0.8V No Effect* Shutdown as the prebias is eliminated, the soft-start cycle begins. No Effect* <0.07V Shutdown During the soft-start cycle, both the PWM and linear out- *No effect means this signal has no effect in shutting down or in enabling the device. puts track the internal soft-start ramp until they reach mid-scale VB. From the mid-scale voltage, the PWM and
OPERATING FREQUENCY
linear outputs are then diverge from each other until the The LTM4663 has a default 2MHz switching frequency for required differential voltage is developed across the TEC the PWM switching regulator output stage. The oscillator or the differential voltage reaches the voltage limit. The is active when the enabled voltage at the EN/SY pin is voltage developed across the TEC depends on the control set to a logic level higher than 2.1V and the V point at that moment. Figure 3 shows an example of the LIM/SD pin voltage is greater than the shutdown threshold of 0.07V. soft-start in cooling mode. Note that, as both the VLDR and VPWM voltages increase with the soft-start ramp and approach V
FREQUENCY SYNCHRONIZATION AND CLOCK IN
B, the ramp slows down to avoid possible cur- rent overshoot at the point where the TEC voltage starts The switching frequency of the LTM4663 can be syn- to build up. chronized to an external clock from 1.85MHz to 3.25MHz Rev. 0 For more information www.analog.com 9 Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Order Information Electrical Characteristics Pin Configuration Typical Performance Characteristics Pin Functions Block Diagram Decoupling Requirements Operation Applications Information Typical Applications Package Description Package Photo Package Description Design Resources Related Parts