Datasheet ADN8835 (Analog Devices) - 3

Data Sheet ADN8835 DETAILED FUNCTIONAL BLOCK DIAGRAM TMPGD VTEC ITEC ADN8835 TEC DRIVER VDD COOLING LINEAR POWER VDD STAGE 5kΩ 20kΩ HEATING PVINL BAND GAP 2.5V 5kΩ VREF VOLTAGE 1.25V 1.25V 1.25V REFERENCE 20kΩ 20kΩ TEC CURRENT SENSE – + LDR VB = 2.5V AT VDD > 4.0V V TEC V B B = 1.5V AT VDD < 4.0V SFB VOLTAGE 2kΩ 80kΩ SENSE VC LDR AGND + TEMPERATURE V – B ERROR LINEAR AMPLIFIER AMPLIFIER PGNDL IN1P VB PGNDL IN1N 80kΩ OUT1 400kΩ SFB 20kΩ 20kΩ 1.25V PWM POWER STAGE 100kΩ PVINS COMPENSATION AMPLIFIER IN2P VC 20kΩ PWM 20kΩ MODULATOR IN2N 20kΩ PWM OUT2 VDD PWM MOSFET SW ERROR DRIVER TEC VOLTAGE CLK 40µA AMPLIFIER V LIMIT AND INTERNAL B SOFT START COOLING OSCILLATOR CLK HEATING PGNDS VHIGH ≥ 2.1V PGNDS VLOW ≤ 0.8V SHUTDOWN ITEC 10µA DEGLITCH TEC CURRENT 0.07V SHUTDOWN LIMIT
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VLIM/SD ILIM EN/SY
14174- Figure 2. Detailed Functional Block Diagram of the ADN8835 Rev. B | Page 3 of 27 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY DETAILED FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE MAXIMUM POWER DISSIPATION ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION ANALOG PID CONTROL DIGITAL PID CONTROL POWERING THE CONTROLLER ENABLE AND SHUTDOWN OSCILLATOR CLOCK FREQUENCY External Clock Operation Connecting Multiple ADN8835 Devices TEMPERATURE LOCK INDICATOR SOFT START ON POWER-UP TEC VOLTAGE/CURRENT MONITOR Voltage Monitor Current Monitor MAXIMUM TEC VOLTAGE LIMIT Using a Resistor Divider to Set the TEC Voltage Limit MAXIMUM TEC CURRENT LIMIT Using a Resistor Divider to Set the TEC Current Limit APPLICATIONS INFORMATION SIGNAL FLOW THERMISTOR SETUP THERMISTOR AMPLIFIER (CHOPPER 1) PID COMPENSATION AMPLIFIER (CHOPPER 2) MOSFET DRIVER AMPLIFIERS PWM OUTPUT FILTER REQUIREMENTS Inductor Selection Capacitor Selection INPUT CAPACITOR SELECTION POWER DISSIPATION PWM Regulator Power Dissipation Conduction Loss (PCOND) Switching Losses (PSW) Transition Losses (PTRAN) Linear Regulator Power Dissipation THERMAL CONSIDERATION PCB LAYOUT GUIDELINES BLOCK DIAGRAMS AND SIGNAL FLOW GUIDELINES FOR REDUCING NOISE AND MINIMIZING POWER LOSS General PCB Layout Guidelines PWM Power Stage Layout Guidelines Linear Power Stage Layout Guidelines Placing the Thermistor Amplifier and PID Components EXAMPLE PCB LAYOUT USING TWO LAYERS OUTLINE DIMENSIONS ORDERING GUIDE