Datasheet ADN8834 (Analog Devices) - 5

Data Sheet ADN8834 Parameter Symbol Test Conditions/Comments Min Typ Max Unit
TEC CURRENT MEASUREMENT (WLCSP) Current Sense Gain R V = 3.3 V 0.525 V/A CS PVIN V = 5 V 0.535 V/A PVIN Current Measurement Accuracy I 700 mA ≤ I ≤ 1.5 A, V = 3.3 V −10 +10 % LDR_ERROR LDR PVIN 800 mA ≤ I ≤ 1.5 A, V = 5 V −10 +10 % LDR PVIN ITEC Voltage Accuracy V V = 3.3 V, cooling, V /2 + 1.597 1.618 1.649 V ITEC_@_700_mA PVIN VREF I × R LDR CS V V = 3.3 V, heating, V /2 − 0.846 0.883 0.891 V ITEC_@_−700_mA PVIN VREF I × R LDR CS V V = 5 V, cooling, V /2 + I × R 1.657 1.678 1.718 V ITEC_@_800_mA PVIN VREF LDR CS V V = 5 V, heating, V /2 − I × R 0.783 0.822 0.836 V ITEC_@_−800_mA PVIN VREF LDR CS TEC CURRENT MEASUREMENT (LFCSP) Current Sense Gain R V = 3.3 V 0.525 V/A CS PVIN V = 5 V 0.525 V/A PVIN Current Measurement Accuracy I 700 mA ≤ I ≤ 1 A, V = 3.3 V −15 +15 % LDR_ERROR LDR PVIN 800 mA ≤ I ≤ 1 A, V = 5 V −15 +15 % LDR PVIN ITEC Voltage Accuracy V V = 3.3 V, cooling, V /2 + I × 1.374 1.618 1.861 V ITEC_@_700_mA PVIN VREF LDR R CS V V = 3.3 V, heating, V /2 − I × 0.750 0.883 1.015 V ITEC_@_−700_mA PVIN VREF LDR R CS V V = 5 V, cooling, V /2 + I × 1.419 1.678 1.921 V ITEC_@_800_mA PVIN VREF LDR R CS V V = 5 V, heating, V /2 − I × 0.705 0.830 0.955 V ITEC_@_−800_mA PVIN VREF LDR R CS ITEC Voltage Output Range V I = 0 A 0 V − V ITEC TEC VREF 0.05 ITEC Bias Voltage V I = 0 A 1.210 1.250 1.285 V ITEC LDR Maximum ITEC Output Current I −2 +2 mA ITEC TEC VOLTAGE MEASUREMENT Voltage Sense Gain A 0.24 0.25 0.26 V/V VTEC Voltage Measurement Accuracy V V – V = 1 V, V + A × 1.475 1.50 1.525 V VTEC_@_1_V LDR SFB VREF/2 VTEC (V – V ) LDR SFB VTEC Output Voltage Range V 0.005 2.625 V VTEC VTEC Bias Voltage V V = V 1.225 1.250 1.285 V VTEC_B LDR SFB Maximum VTEC Output Current R −2 +2 mA VTEC TEMPERATURE GOOD (LFCSP Only) TMPGD Low Output Voltage V No load 0.4 V TMPGD_LO TMPGD High Output Voltage V No load 2.0 V TMPGD_HO TMPGD Output Low Impedance R 25 Ω TMPGD_LOW TMPGD Output High Impedance R 50 Ω TMPGD_LOW High Threshold V IN2N tied to OUT2, V = 1.5 V 1.54 1.56 V OUT1_THH IN2P Low Threshold V IN2N tied to OUT2, V = 1.5 V 1.40 1.46 V OUT1_THL IN2P INTERNAL SOFT START Soft Start Time t 150 ms SS VLIM/SD SHUTDOWN VLIM/SD Low Voltage Threshold V 0.07 V VLIM/SD_THL THERMAL SHUTDOWN Thermal Shutdown Threshold T 170 °C SHDN_TH Thermal Shutdown Hysteresis T 17 °C SHDN_HYS 1 This specification is guaranteed by design. 2 This specification is guaranteed by characterization. Rev. B | Page 5 of 27 Document Outline Features Applications Functional Block Diagram General Description Revision History Specifications Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configurations and Function Descriptions Typical Performance Characteristics Detailed Functional Block Diagram Theory of Operation Analog PID Control Digital PID Control Powering the Controller Enable and Shutdown Oscillator Clock Frequency External Clock Operation Connecting Multiple ADN8834 Devices Temperature Lock Indicator (LFCSP Only) Soft Start on Power-Up TEC Voltage/Current Monitor Voltage Monitor Current Monitor Maximum TEC Voltage Limit Using a Resistor Divider to Set the TEC Voltage Limit Maximum TEC Current Limit Using a Resistor Divider to Set the TEC Current Limit Applications Information Signal Flow Thermistor Setup Thermistor Amplifier (Chopper 1) PID Compensation Amplifier (Chopper 2) MOSFET Driver Amplifiers PWM Output Filter Requirements Inductor Selection Capacitor Selection Input Capacitor Selection Power Dissipation PWM Regulator Power Dissipation Conduction Loss (PCOND) Switching Loss (PSW) Transition Loss (PTRAN) Linear Regulator Power Dissipation PCB Layout Guidelines Block Diagrams and Signal Flow Guidelines for Reducing Noise and Minimizing Power Loss General PCB Layout Guidelines PWM Power Stage Layout Guidelines Linear Power Stage Layout Guidelines Placing the Thermistor Amplifier and PID Components Example PCB Layout Using Two Layers Outline Dimensions Ordering Guide