Datasheet ADN8831 (Analog Devices) - 4

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ADN8831 Data Sheet SPECIFICATIONS ELECTRICAL CHARACTERISTICS
VDD = 3.0 V to 5.0 V, TA = 25°C, unless otherwise noted.
Table 1. Parameter1 S ymbol Test Conditions/Comments Min Typ Max Unit
PWM OUTPUT DRIVER Output Transition Time tR, tF CL = 3300 pF 20 ns Nonoverlapping Clock Delay 40 80 ns Output Resistance RO (SNGATE, SPGATE) IL = 10 mA, VDD = 3.0 V 6 Ω Output Voltage Swing2 SFB VLIM = VREF 0 VDD V LINEAR OUTPUT AMPLIFIER Output Resistance RO, LNGATE IOUT = 2 mA, VDD = 3.0 V 200 Ω RO, LPGATE IOUT = 2 mA, VDD = 3.0 V 100 Ω Output Voltage Swing2 LFB 0 VDD V POWER SUPPLY Power Supply Voltage VDD 3.0 5.5 V Supply Current ISY PWM not switching 8 12 mA −40°C ≤ TA ≤ +85°C 15 mA Shutdown Current ISD SYNCI/SD = 0 V 8 μA Soft Start Charging Current ISS VSS = 0 V 8 μA Undervoltage Lockout3 UVLO Low to high threshold 2.2 2.6 V Standby Current ISB SYNCI/SD = VDD, SS/SB = 0 V 2 mA Standby Threshold VSB SYNCI/SD = VDD 150 200 mV ERROR/COMPENSATION AMPLIFIERS Input Offset Voltage VOS1 VCM1 = 1.5 V, VIN1P − VIN1M 10 100 μV VOS2 VCM2 = 1.5 V, VIN2P − VIN2M 10 100 μV Input Voltage Range VCM1, VCM2 0 VDD V Common-Mode Rejection Ratio CMRR1, CMRR2 VCM1, VCM2 = 0.2 V to VDD − 0.2 V 120 dB Output Voltage High VOH1, VOH2 VDD − 0.03 V Output Voltage Low VOL1, VOL2 25 mV Power Supply Rejection Ratio PSRR1, PSRR2 3.0 V ≤ VDD ≤ 5.0 V 110 dB Output Current IOUT1, IOUT2 Sourcing and sinking 5 mA Gain Bandwidth Product GBW1, GBW2 VOUT = 0.5 V to (VDD − 1 V) 2 MHz OSCILLATOR Sync Range fCLK SYNCI/SD connected to external 300 1000 kHz clock Oscillator Frequency fCLK COMPOSC = VDD, RFREQ = 118 kΩ, 800 1000 1250 kHz SYNCI/SD = VDD, VDD = 5.0 V Nominal Free-Run Oscillation fCLK-NOMINAL COMPOSC = VDD, SYNCI/SD = VDD 200 1000 kHz Frequency Phase Adjustment Range2 ΦCLK VPHASE = 0.13 V, fSYNCI/ = 1 MHz 50 Degrees SD VPHASE = 2.3 V, fSYNCI/SD = 1 MHz 330 Degrees Phase Adjustment Default ΦCLK PHASE = open 180 Degrees REFERENCE VOLTAGE Reference Voltage VREF IREF = 2 mA 2.35 V IREF = 0 mA 2.37 2.47 2.57 V Rev. C | Page 4 of 18 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM REVISION HISTORY DETAILED BLOCK DIAGRAM SPECIFICATIONS ELECTRICAL CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION OSCILLATOR CLOCK FREQUENCY Free-Run Operation External Clock Operation Connecting Multiple ADN8831 Devices OSCILLATOR CLOCK PHASE TEMPERATURE LOCK INDICATOR SOFT START ON POWER-UP SHUTDOWN MODE STANDBY MODE TEC VOLTAGE/CURRENT MONITOR Voltage Monitor Current Monitor MAXIMUM TEC VOLTAGE LIMIT Using a DAC Using a Resistor Divider MAXIMUM TEC CURRENT LIMIT APPLICATIONS INFORMATION SIGNAL FLOW THERMISTOR SETUP THERMISTOR AMPLIFIER (Chop1) PID COMPENSATION AMPLIFIER (Chop2) MOSFET DRIVER AMPLIFIER OUTLINE DIMENSIONS ORDERING GUIDE