Preliminary Datasheet MB85RS4MTY (Fujitsu) - 9
| Manufacturer | Fujitsu |
| Description | Memory FRAM 4M (512 K х 8) Bit SPI |
| Pages / Page | 39 / 9 — MB85RS4MTY. RDSR. WRSR |
| File Format / Size | PDF / 2.6 Mb |
| Document Language | English |
MB85RS4MTY. RDSR. WRSR
Model Line for this Datasheet
Text Version of Document
MB85RS4MTY RDSR
The RDSR command reads status register data. After op-code of RDSR is input to SI, 8-cycle clock is input to SCK. The SI value is invalid for this time. SO is output synchronously to a falling edge of SCK. In the RDSR command, repeated reading of status register is enabled by sending SCK continuously before rising of CS. CS 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 SCK SI 0 0 0 0 0 1 0 1 Invalid Data Out High-Z SO Invalid MSB LSB
WRSR
The WRSR command writes data to the nonvolatile memory bit of status register. After performing WRSR op-code to a SI pin, 8 bits writing data is input. WEL (Write Enable Latch) is not able to be written with WRSR command. A SI value correspondent to bit 1 is ignored. Bit 0 of the status register is fixed to “0” and cannot be written. The SI value corresponding to bit 0 is ignored. WP signal level shall be fixed before performing WRSR command, and do not change the WP signal level until the end of command sequence. CS 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 SCK Instruction Data In SI 0 0 0 0 0 0 0 1 7 6 5 4 3 2 1 0 MSB LSB High-Z SO DS501-00065-0v1-E 9 Document Outline DESCRIPTION FEATURES PIN ASSIGNMENT PIN FUNCTIONAL DESCRIPTIONS BLOCK DIAGRAM SPI MODE SERIAL PERIPHERAL INTERFACE (SPI) STATUS REGISTER OP-CODE COMMAND BLOCK PROTECT WRITING PROTECT ABSOLUTE MAXIMUM RATINGS RECOMMENDED OPERATING CONDITIONS ELECTRICAL CHARACTERISTICS 1. DC Characteristics 2. AC Characteristics 3. Pin Capacitance TIMING DIAGRAM POWER ON/OFF SEQUENCE FRAM CHARACTERISTICS NOTE ON USE ESD AND LATCH-UP REFLOW CONDITIONS AND FLOOR LIFE Current status on Contained Restricted Substances ORDERING INFORMATION PACKAGE DIMENSION MARKING (Example) PACKING INFORMATION 1. Tube 2. Emboss Tape
The RDSR command reads status register data. After op-code of RDSR is input to SI, 8-cycle clock is input to SCK. The SI value is invalid for this time. SO is output synchronously to a falling edge of SCK. In the RDSR command, repeated reading of status register is enabled by sending SCK continuously before rising of CS. CS 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 SCK SI 0 0 0 0 0 1 0 1 Invalid Data Out High-Z SO Invalid MSB LSB
WRSR
The WRSR command writes data to the nonvolatile memory bit of status register. After performing WRSR op-code to a SI pin, 8 bits writing data is input. WEL (Write Enable Latch) is not able to be written with WRSR command. A SI value correspondent to bit 1 is ignored. Bit 0 of the status register is fixed to “0” and cannot be written. The SI value corresponding to bit 0 is ignored. WP signal level shall be fixed before performing WRSR command, and do not change the WP signal level until the end of command sequence. CS 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 SCK Instruction Data In SI 0 0 0 0 0 0 0 1 7 6 5 4 3 2 1 0 MSB LSB High-Z SO DS501-00065-0v1-E 9 Document Outline DESCRIPTION FEATURES PIN ASSIGNMENT PIN FUNCTIONAL DESCRIPTIONS BLOCK DIAGRAM SPI MODE SERIAL PERIPHERAL INTERFACE (SPI) STATUS REGISTER OP-CODE COMMAND BLOCK PROTECT WRITING PROTECT ABSOLUTE MAXIMUM RATINGS RECOMMENDED OPERATING CONDITIONS ELECTRICAL CHARACTERISTICS 1. DC Characteristics 2. AC Characteristics 3. Pin Capacitance TIMING DIAGRAM POWER ON/OFF SEQUENCE FRAM CHARACTERISTICS NOTE ON USE ESD AND LATCH-UP REFLOW CONDITIONS AND FLOOR LIFE Current status on Contained Restricted Substances ORDERING INFORMATION PACKAGE DIMENSION MARKING (Example) PACKING INFORMATION 1. Tube 2. Emboss Tape
