Datasheet nRF52840 (Nordic Semiconductor) - 6

link to page 135 link to page 136 link to page 136 link to page 136 link to page 137 link to page 137 link to page 138 link to page 138 link to page 139 link to page 142 link to page 142 link to page 142 link to page 142 link to page 143 link to page 145 link to page 146 link to page 146 link to page 148 link to page 148 link to page 149 link to page 151 link to page 156 link to page 157 link to page 157 link to page 158 link to page 158 link to page 159 link to page 163 link to page 163 link to page 164 link to page 164 link to page 165 link to page 165 link to page 166 link to page 166 link to page 168 link to page 170 link to page 172 link to page 173 link to page 182 link to page 183 link to page 184 link to page 184 link to page 185 link to page 191 link to page 191 link to page 192 link to page 205 link to page 206 link to page 208 link to page 209 link to page 209 link to page 210 link to page 211 6.6 CRYPTOCELL — ARM TrustZone CryptoCell 310 . 135 6.6.1 Usage . 136 6.6.2 Always-on (AO) power domain . 136 6.6.3 Lifecycle state (LCS) . 136 6.6.4 Cryptographic key selection . 137 6.6.5 Direct memory access (DMA) . 137 6.6.6 Standards . 138 6.6.7 Registers . 138 6.6.8 Host interface . 139 6.7 ECB — AES electronic codebook mode encryption . 142 6.7.1 Shared resources . 142 6.7.2 EasyDMA . 142 6.7.3 ECB data structure . 142 6.7.4 Registers . 143 6.7.5 Electrical specification . 145 6.8 EGU — Event generator unit . 146 6.8.1 Registers . 146 6.8.2 Electrical specification . 148 6.9 GPIO — General purpose input/output . 148 6.9.1 Pin configuration . 149 6.9.2 Registers . 151 6.9.3 Electrical specification . 156 6.10 GPIOTE — GPIO tasks and events . 157 6.10.1 Pin events and tasks . 157 6.10.2 Port event . 158 6.10.3 Tasks and events pin configuration . 158 6.10.4 Registers . 159 6.10.5 Electrical specification . 163 6.11 I2S — Inter-IC sound interface . 163 6.11.1 Mode . 164 6.11.2 Transmitting and receiving . 164 6.11.3 Left right clock (LRCK) . 165 6.11.4 Serial clock (SCK) . 165 6.11.5 Master clock (MCK) . 166 6.11.6 Width, alignment and format . 166 6.11.7 EasyDMA . 168 6.11.8 Module operation . 170 6.11.9 Pin configuration . 172 6.11.10 Registers . 173 6.11.11 Electrical specification . 182 6.12 LPCOMP — Low power comparator . 183 6.12.1 Shared resources . 184 6.12.2 Pin configuration . 184 6.12.3 Registers . 185 6.12.4 Electrical specification . 191 6.13 MWU — Memory watch unit . 191 6.13.1 Registers . 192 6.14 NFCT — Near field communication tag . 205 6.14.1 Overview . 206 6.14.2 Operating states . 208 6.14.3 Pin configuration . 209 6.14.4 EasyDMA . 209 6.14.5 Frame assembler . 210 6.14.6 Frame disassembler . 211 4413_417 v1.1 vi Document Outline Contents Feature list Revision history About this document 2.1 Document naming and status 2.2 Peripheral naming and abbreviations 2.3 Register tables 2.3.1 Fields and values 2.4 Registers 2.4.1 DUMMY Block diagram Core components 4.1 CPU 4.1.1 Floating point interrupt 4.1.2 CPU and support module configuration 4.1.3 Electrical specification 4.1.3.1 CPU performance 4.2 Memory 4.2.1 RAM - Random access memory 4.2.2 Flash - Non-volatile memory 4.2.3 Memory map 4.2.4 Instantiation 4.3 NVMC — Non-volatile memory controller 4.3.1 Writing to flash 4.3.2 Erasing a page in flash 4.3.3 Writing to user information configuration registers (UICR) 4.3.4 Erasing user information configuration registers (UICR) 4.3.5 Erase all 4.3.6 Access port protection behavior 4.3.7 Partial erase of a page in flash 4.3.8 Cache 4.3.9 Registers 4.3.9.1 READY 4.3.9.2 READYNEXT 4.3.9.3 CONFIG 4.3.9.4 ERASEPAGE 4.3.9.5 ERASEPCR1 ( Deprecated ) 4.3.9.6 ERASEALL 4.3.9.7 ERASEPCR0 ( Deprecated ) 4.3.9.8 ERASEUICR 4.3.9.9 ERASEPAGEPARTIAL 4.3.9.10 ERASEPAGEPARTIALCFG 4.3.9.11 ICACHECNF 4.3.9.12 IHIT 4.3.9.13 IMISS 4.3.10 Electrical specification 4.3.10.1 Flash programming 4.3.10.2 Cache size 4.4 FICR — Factory information configuration registers 4.4.1 Registers 4.4.1.1 CODEPAGESIZE 4.4.1.2 CODESIZE 4.4.1.3 DEVICEID[n] (n=0..1) 4.4.1.4 ER[n] (n=0..3) 4.4.1.5 IR[n] (n=0..3) 4.4.1.6 DEVICEADDRTYPE 4.4.1.7 DEVICEADDR[n] (n=0..1) 4.4.1.8 INFO.PART 4.4.1.9 INFO.VARIANT 4.4.1.10 INFO.PACKAGE 4.4.1.11 INFO.RAM 4.4.1.12 INFO.FLASH 4.4.1.13 PRODTEST[n] (n=0..2) 4.4.1.14 TEMP.A0 4.4.1.15 TEMP.A1 4.4.1.16 TEMP.A2 4.4.1.17 TEMP.A3 4.4.1.18 TEMP.A4 4.4.1.19 TEMP.A5 4.4.1.20 TEMP.B0 4.4.1.21 TEMP.B1 4.4.1.22 TEMP.B2 4.4.1.23 TEMP.B3 4.4.1.24 TEMP.B4 4.4.1.25 TEMP.B5 4.4.1.26 TEMP.T0 4.4.1.27 TEMP.T1 4.4.1.28 TEMP.T2 4.4.1.29 TEMP.T3 4.4.1.30 TEMP.T4 4.4.1.31 NFC.TAGHEADER0 4.4.1.32 NFC.TAGHEADER1 4.4.1.33 NFC.TAGHEADER2 4.4.1.34 NFC.TAGHEADER3 4.4.1.35 TRNG90B.BYTES 4.4.1.36 TRNG90B.RCCUTOFF 4.4.1.37 TRNG90B.APCUTOFF 4.4.1.38 TRNG90B.STARTUP 4.4.1.39 TRNG90B.ROSC1 4.4.1.40 TRNG90B.ROSC2 4.4.1.41 TRNG90B.ROSC3 4.4.1.42 TRNG90B.ROSC4 4.5 UICR — User information configuration registers 4.5.1 Registers 4.5.1.1 NRFFW[n] (n=0..12) 4.5.1.2 NRFHW[n] (n=0..11) 4.5.1.3 CUSTOMER[n] (n=0..31) 4.5.1.4 PSELRESET[n] (n=0..1) 4.5.1.5 APPROTECT 4.5.1.6 NFCPINS 4.5.1.7 DEBUGCTRL 4.5.1.8 REGOUT0 4.6 EasyDMA 4.6.1 EasyDMA error handling 4.6.2 EasyDMA array list 4.7 AHB multilayer 4.8 Debug and trace 4.8.1 DAP - Debug access port 4.8.2 CTRL-AP - Control access port 4.8.2.1 Registers 4.8.2.1.1 RESET 4.8.2.1.2 ERASEALL 4.8.2.1.3 ERASEALLSTATUS 4.8.2.1.4 APPROTECTSTATUS 4.8.2.1.5 IDR 4.8.2.2 Electrical specification 4.8.2.2.1 Control access port 4.8.3 Debug interface mode 4.8.4 Real-time debug 4.8.5 Trace 4.8.5.1 Electrical specification 4.8.5.1.1 Trace port Power and clock management 5.1 Power management unit (PMU) 5.2 Current consumption 5.2.1 Electrical specification 5.2.1.1 Sleep 5.2.1.2 COMP active 5.2.1.3 CPU running 5.2.1.4 NFCT active 5.2.1.5 Radio transmitting/receiving 5.2.1.6 RNG active 5.2.1.7 SAADC active 5.2.1.8 TEMP active 5.2.1.9 TIMER running 5.2.1.10 WDT active 5.2.1.11 Compounded 5.3 POWER — Power supply 5.3.1 Main supply 5.3.1.1 Main voltage regulators 5.3.1.2 GPIO levels 5.3.1.3 External circuitry supply 5.3.1.4 Regulator configuration examples 5.3.1.5 Power supply supervisor 5.3.1.6 Power-fail comparator 5.3.2 USB supply 5.3.3 System OFF mode 5.3.3.1 Emulated System OFF mode 5.3.4 System ON mode 5.3.4.1 Sub power modes 5.3.5 RAM power control 5.3.6 Reset 5.3.6.1 Power-on reset 5.3.6.2 Pin reset 5.3.6.3 Wakeup from System OFF mode reset 5.3.6.4 Soft reset 5.3.6.5 Watchdog reset 5.3.6.6 Brownout reset 5.3.6.7 Retained registers 5.3.6.8 Reset behavior 5.3.7 Registers 5.3.7.1 TASKS_CONSTLAT 5.3.7.2 TASKS_LOWPWR 5.3.7.3 EVENTS_POFWARN 5.3.7.4 EVENTS_SLEEPENTER 5.3.7.5 EVENTS_SLEEPEXIT 5.3.7.6 EVENTS_USBDETECTED 5.3.7.7 EVENTS_USBREMOVED 5.3.7.8 EVENTS_USBPWRRDY 5.3.7.9 INTENSET 5.3.7.10 INTENCLR 5.3.7.11 RESETREAS 5.3.7.12 RAMSTATUS ( Deprecated ) 5.3.7.13 USBREGSTATUS 5.3.7.14 SYSTEMOFF 5.3.7.15 POFCON 5.3.7.16 GPREGRET 5.3.7.17 GPREGRET2 5.3.7.18 DCDCEN 5.3.7.19 DCDCEN0 5.3.7.20 MAINREGSTATUS 5.3.7.21 RAM[n].POWER (n=0..8) 5.3.7.22 RAM[n].POWERSET (n=0..8) 5.3.7.23 RAM[n].POWERCLR (n=0..8) 5.3.8 Electrical specification 5.3.8.1 Regulator operating conditions 5.3.8.2 Regulator specifications, REG0 stage 5.3.8.3 Device startup times 5.3.8.4 Power fail comparator 5.3.8.5 USB operating conditions 5.3.8.6 USB regulator specifications 5.3.8.7 VBUS detection specifications 5.4 CLOCK — Clock control 5.4.1 HFCLK controller 5.4.1.1 64 MHz crystal oscillator (HFXO) 5.4.2 LFCLK controller 5.4.2.1 32.768 kHz RC oscillator (LFRC) 5.4.2.2 Calibrating the 32.768 kHz RC oscillator 5.4.2.3 Calibration timer 5.4.2.4 32.768 kHz crystal oscillator (LFXO) 5.4.2.5 32.768 kHz synthesized from HFCLK (LFSYNT) 5.4.3 Registers 5.4.3.1 TASKS_HFCLKSTART 5.4.3.2 TASKS_HFCLKSTOP 5.4.3.3 TASKS_LFCLKSTART 5.4.3.4 TASKS_LFCLKSTOP 5.4.3.5 TASKS_CAL 5.4.3.6 TASKS_CTSTART 5.4.3.7 TASKS_CTSTOP 5.4.3.8 EVENTS_HFCLKSTARTED 5.4.3.9 EVENTS_LFCLKSTARTED 5.4.3.10 EVENTS_DONE 5.4.3.11 EVENTS_CTTO 5.4.3.12 EVENTS_CTSTARTED 5.4.3.13 EVENTS_CTSTOPPED 5.4.3.14 INTENSET 5.4.3.15 INTENCLR 5.4.3.16 HFCLKRUN 5.4.3.17 HFCLKSTAT 5.4.3.18 LFCLKRUN 5.4.3.19 LFCLKSTAT 5.4.3.20 LFCLKSRCCOPY 5.4.3.21 LFCLKSRC 5.4.3.22 HFXODEBOUNCE 5.4.3.23 CTIV ( Retained ) 5.4.3.24 TRACECONFIG 5.4.3.25 LFRCMODE 5.4.4 Electrical specification 5.4.4.1 64 MHz internal oscillator (HFINT) 5.4.4.2 64 MHz crystal oscillator (HFXO) 5.4.4.3 Low frequency crystal oscillator (LFXO) 5.4.4.4 Low frequency RC oscillator (LFRC), Normal mode 5.4.4.5 Low frequency RC oscillator (LFRC), Ultra-low power mode (ULP) 5.4.4.6 Synthesized low frequency clock (LFSYNT) Peripherals 6.1 Peripheral interface 6.1.1 Peripheral ID 6.1.2 Peripherals with shared ID 6.1.3 Peripheral registers 6.1.4 Bit set and clear 6.1.5 Tasks 6.1.6 Events 6.1.7 Shortcuts 6.1.8 Interrupts 6.2 AAR — Accelerated address resolver 6.2.1 EasyDMA 6.2.2 Resolving a resolvable address 6.2.3 Use case example for chaining RADIO packet reception with address resolution using AAR 6.2.4 IRK data structure 6.2.5 Registers 6.2.5.1 TASKS_START 6.2.5.2 TASKS_STOP 6.2.5.3 EVENTS_END 6.2.5.4 EVENTS_RESOLVED 6.2.5.5 EVENTS_NOTRESOLVED 6.2.5.6 INTENSET 6.2.5.7 INTENCLR 6.2.5.8 STATUS 6.2.5.9 ENABLE 6.2.5.10 NIRK 6.2.5.11 IRKPTR 6.2.5.12 ADDRPTR 6.2.5.13 SCRATCHPTR 6.2.6 Electrical specification 6.2.6.1 AAR Electrical Specification 6.3 ACL — Access control lists 6.3.1 Registers 6.3.1.1 ACL[n].ADDR (n=0..7) 6.3.1.2 ACL[n].SIZE (n=0..7) 6.3.1.3 ACL[n].PERM (n=0..7) 6.4 CCM — AES CCM mode encryption 6.4.1 Key-steam generation 6.4.2 Encryption 6.4.3 Decryption 6.4.4 AES CCM and RADIO concurrent operation 6.4.5 Encrypting packets on-the-fly in radio transmit mode 6.4.6 Decrypting packets on-the-fly in radio receive mode 6.4.7 CCM data structure 6.4.8 EasyDMA and ERROR event 6.4.9 Registers 6.4.9.1 TASKS_KSGEN 6.4.9.2 TASKS_CRYPT 6.4.9.3 TASKS_STOP 6.4.9.4 TASKS_RATEOVERRIDE 6.4.9.5 EVENTS_ENDKSGEN 6.4.9.6 EVENTS_ENDCRYPT 6.4.9.7 EVENTS_ERROR ( Deprecated ) 6.4.9.8 SHORTS 6.4.9.9 INTENSET 6.4.9.10 INTENCLR 6.4.9.11 MICSTATUS 6.4.9.12 ENABLE 6.4.9.13 MODE 6.4.9.14 CNFPTR 6.4.9.15 INPTR 6.4.9.16 OUTPTR 6.4.9.17 SCRATCHPTR 6.4.9.18 MAXPACKETSIZE 6.4.9.19 RATEOVERRIDE 6.4.10 Electrical specification 6.4.10.1 Timing specification 6.5 COMP — Comparator 6.5.1 Differential mode 6.5.2 Single-ended mode 6.5.3 Registers 6.5.3.1 TASKS_START 6.5.3.2 TASKS_STOP 6.5.3.3 TASKS_SAMPLE 6.5.3.4 EVENTS_READY 6.5.3.5 EVENTS_DOWN 6.5.3.6 EVENTS_UP 6.5.3.7 EVENTS_CROSS 6.5.3.8 SHORTS 6.5.3.9 INTEN 6.5.3.10 INTENSET 6.5.3.11 INTENCLR 6.5.3.12 RESULT 6.5.3.13 ENABLE 6.5.3.14 PSEL 6.5.3.15 REFSEL 6.5.3.16 EXTREFSEL 6.5.3.17 TH 6.5.3.18 MODE 6.5.3.19 HYST 6.5.4 Electrical specification 6.5.4.1 COMP Electrical Specification 6.6 CRYPTOCELL — ARM TrustZone CryptoCell 310 6.6.1 Usage 6.6.2 Always-on (AO) power domain 6.6.3 Lifecycle state (LCS) 6.6.4 Cryptographic key selection 6.6.4.1 RTL key 6.6.4.2 Device root key 6.6.5 Direct memory access (DMA) 6.6.6 Standards 6.6.7 Registers 6.6.7.1 ENABLE 6.6.8 Host interface 6.6.8.1 HOST_RGF block 6.6.8.1.1 Registers 6.6.8.1.1.1 HOST_CRYPTOKEY_SEL 6.6.8.1.1.2 HOST_IOT_KPRTL_LOCK 6.6.8.1.1.3 HOST_IOT_KDR0 6.6.8.1.1.4 HOST_IOT_KDR1 6.6.8.1.1.5 HOST_IOT_KDR2 6.6.8.1.1.6 HOST_IOT_KDR3 6.6.8.1.1.7 HOST_IOT_LCS 6.7 ECB — AES electronic codebook mode encryption 6.7.1 Shared resources 6.7.2 EasyDMA 6.7.3 ECB data structure 6.7.4 Registers 6.7.4.1 TASKS_STARTECB 6.7.4.2 TASKS_STOPECB 6.7.4.3 EVENTS_ENDECB 6.7.4.4 EVENTS_ERRORECB 6.7.4.5 INTENSET 6.7.4.6 INTENCLR 6.7.4.7 ECBDATAPTR 6.7.5 Electrical specification 6.7.5.1 ECB Electrical Specification 6.8 EGU — Event generator unit 6.8.1 Registers 6.8.1.1 TASKS_TRIGGER[n] (n=0..15) 6.8.1.2 EVENTS_TRIGGERED[n] (n=0..15) 6.8.1.3 INTEN 6.8.1.4 INTENSET 6.8.1.5 INTENCLR 6.8.2 Electrical specification 6.8.2.1 EGU Electrical Specification 6.9 GPIO — General purpose input/output 6.9.1 Pin configuration 6.9.2 Registers 6.9.2.1 OUT 6.9.2.2 OUTSET 6.9.2.3 OUTCLR 6.9.2.4 IN 6.9.2.5 DIR 6.9.2.6 DIRSET 6.9.2.7 DIRCLR 6.9.2.8 LATCH 6.9.2.9 DETECTMODE 6.9.2.10 PIN_CNF[n] (n=0..31) 6.9.3 Electrical specification 6.9.3.1 GPIO Electrical Specification 6.10 GPIOTE — GPIO tasks and events 6.10.1 Pin events and tasks 6.10.2 Port event 6.10.3 Tasks and events pin configuration 6.10.4 Registers 6.10.4.1 TASKS_OUT[n] (n=0..7) 6.10.4.2 TASKS_SET[n] (n=0..7) 6.10.4.3 TASKS_CLR[n] (n=0..7) 6.10.4.4 EVENTS_IN[n] (n=0..7) 6.10.4.5 EVENTS_PORT 6.10.4.6 INTENSET 6.10.4.7 INTENCLR 6.10.4.8 CONFIG[n] (n=0..7) 6.10.5 Electrical specification 6.11 I2S — Inter-IC sound interface 6.11.1 Mode 6.11.2 Transmitting and receiving 6.11.3 Left right clock (LRCK) 6.11.4 Serial clock (SCK) 6.11.5 Master clock (MCK) 6.11.6 Width, alignment and format 6.11.7 EasyDMA 6.11.8 Module operation 6.11.9 Pin configuration 6.11.10 Registers 6.11.10.1 TASKS_START 6.11.10.2 TASKS_STOP 6.11.10.3 EVENTS_RXPTRUPD 6.11.10.4 EVENTS_STOPPED 6.11.10.5 EVENTS_TXPTRUPD 6.11.10.6 INTEN 6.11.10.7 INTENSET 6.11.10.8 INTENCLR 6.11.10.9 ENABLE 6.11.10.10 CONFIG.MODE 6.11.10.11 CONFIG.RXEN 6.11.10.12 CONFIG.TXEN 6.11.10.13 CONFIG.MCKEN 6.11.10.14 CONFIG.MCKFREQ 6.11.10.15 CONFIG.RATIO 6.11.10.16 CONFIG.SWIDTH 6.11.10.17 CONFIG.ALIGN 6.11.10.18 CONFIG.FORMAT 6.11.10.19 CONFIG.CHANNELS 6.11.10.20 RXD.PTR 6.11.10.21 TXD.PTR 6.11.10.22 RXTXD.MAXCNT 6.11.10.23 PSEL.MCK 6.11.10.24 PSEL.SCK 6.11.10.25 PSEL.LRCK 6.11.10.26 PSEL.SDIN 6.11.10.27 PSEL.SDOUT 6.11.11 Electrical specification 6.11.11.1 I2S timing specification 6.12 LPCOMP — Low power comparator 6.12.1 Shared resources 6.12.2 Pin configuration 6.12.3 Registers 6.12.3.1 TASKS_START 6.12.3.2 TASKS_STOP 6.12.3.3 TASKS_SAMPLE 6.12.3.4 EVENTS_READY 6.12.3.5 EVENTS_DOWN 6.12.3.6 EVENTS_UP 6.12.3.7 EVENTS_CROSS 6.12.3.8 SHORTS 6.12.3.9 INTENSET 6.12.3.10 INTENCLR 6.12.3.11 RESULT 6.12.3.12 ENABLE 6.12.3.13 PSEL 6.12.3.14 REFSEL 6.12.3.15 EXTREFSEL 6.12.3.16 ANADETECT 6.12.3.17 HYST 6.12.4 Electrical specification 6.12.4.1 LPCOMP Electrical Specification 6.13 MWU — Memory watch unit 6.13.1 Registers 6.13.1.1 EVENTS_REGION[n].WA (n=0..3) 6.13.1.2 EVENTS_REGION[n].RA (n=0..3) 6.13.1.3 EVENTS_PREGION[n].WA (n=0..1) 6.13.1.4 EVENTS_PREGION[n].RA (n=0..1) 6.13.1.5 INTEN 6.13.1.6 INTENSET 6.13.1.7 INTENCLR 6.13.1.8 NMIEN 6.13.1.9 NMIENSET 6.13.1.10 NMIENCLR 6.13.1.11 PERREGION[n].SUBSTATWA (n=0..1) 6.13.1.12 PERREGION[n].SUBSTATRA (n=0..1) 6.13.1.13 REGIONEN 6.13.1.14 REGIONENSET 6.13.1.15 REGIONENCLR 6.13.1.16 REGION[n].START (n=0..3) 6.13.1.17 REGION[n].END (n=0..3) 6.13.1.18 PREGION[n].START (n=0..1) 6.13.1.19 PREGION[n].END (n=0..1) 6.13.1.20 PREGION[n].SUBS (n=0..1) 6.14 NFCT — Near field communication tag 6.14.1 Overview 6.14.2 Operating states 6.14.3 Pin configuration 6.14.4 EasyDMA 6.14.5 Frame assembler 6.14.6 Frame disassembler 6.14.7 Frame timing controller 6.14.8 Collision resolution 6.14.9 Antenna interface 6.14.10 NFCT antenna recommendations 6.14.11 Battery protection 6.14.12 References 6.14.13 Registers 6.14.13.1 TASKS_ACTIVATE 6.14.13.2 TASKS_DISABLE 6.14.13.3 TASKS_SENSE 6.14.13.4 TASKS_STARTTX 6.14.13.5 TASKS_ENABLERXDATA 6.14.13.6 TASKS_GOIDLE 6.14.13.7 TASKS_GOSLEEP 6.14.13.8 EVENTS_READY 6.14.13.9 EVENTS_FIELDDETECTED 6.14.13.10 EVENTS_FIELDLOST 6.14.13.11 EVENTS_TXFRAMESTART 6.14.13.12 EVENTS_TXFRAMEEND 6.14.13.13 EVENTS_RXFRAMESTART 6.14.13.14 EVENTS_RXFRAMEEND 6.14.13.15 EVENTS_ERROR 6.14.13.16 EVENTS_RXERROR 6.14.13.17 EVENTS_ENDRX 6.14.13.18 EVENTS_ENDTX 6.14.13.19 EVENTS_AUTOCOLRESSTARTED 6.14.13.20 EVENTS_COLLISION 6.14.13.21 EVENTS_SELECTED 6.14.13.22 EVENTS_STARTED 6.14.13.23 SHORTS 6.14.13.24 INTEN 6.14.13.25 INTENSET 6.14.13.26 INTENCLR 6.14.13.27 ERRORSTATUS 6.14.13.28 FRAMESTATUS.RX 6.14.13.29 NFCTAGSTATE 6.14.13.30 SLEEPSTATE 6.14.13.31 FIELDPRESENT 6.14.13.32 FRAMEDELAYMIN 6.14.13.33 FRAMEDELAYMAX 6.14.13.34 FRAMEDELAYMODE 6.14.13.35 PACKETPTR 6.14.13.36 MAXLEN 6.14.13.37 TXD.FRAMECONFIG 6.14.13.38 TXD.AMOUNT 6.14.13.39 RXD.FRAMECONFIG 6.14.13.40 RXD.AMOUNT 6.14.13.41 NFCID1_LAST 6.14.13.42 NFCID1_2ND_LAST 6.14.13.43 NFCID1_3RD_LAST 6.14.13.44 AUTOCOLRESCONFIG 6.14.13.45 SENSRES 6.14.13.46 SELRES 6.14.14 Electrical specification 6.14.14.1 NFCT Electrical Specification 6.14.14.2 NFCT Timing Parameters 6.15 PDM — Pulse density modulation interface 6.15.1 Master clock generator 6.15.2 Module operation 6.15.3 Decimation filter 6.15.4 EasyDMA 6.15.5 Hardware example 6.15.6 Pin configuration 6.15.7 Registers 6.15.7.1 TASKS_START 6.15.7.2 TASKS_STOP 6.15.7.3 EVENTS_STARTED 6.15.7.4 EVENTS_STOPPED 6.15.7.5 EVENTS_END 6.15.7.6 INTEN 6.15.7.7 INTENSET 6.15.7.8 INTENCLR 6.15.7.9 ENABLE 6.15.7.10 PDMCLKCTRL 6.15.7.11 MODE 6.15.7.12 GAINL 6.15.7.13 GAINR 6.15.7.14 RATIO 6.15.7.15 PSEL.CLK 6.15.7.16 PSEL.DIN 6.15.7.17 SAMPLE.PTR 6.15.7.18 SAMPLE.MAXCNT 6.15.8 Electrical specification 6.15.8.1 PDM Electrical Specification 6.16 PPI — Programmable peripheral interconnect 6.16.1 Pre-programmed channels 6.16.2 Registers 6.16.2.1 TASKS_CHG[n].EN (n=0..5) 6.16.2.2 TASKS_CHG[n].DIS (n=0..5) 6.16.2.3 CHEN 6.16.2.4 CHENSET 6.16.2.5 CHENCLR 6.16.2.6 CH[n].EEP (n=0..19) 6.16.2.7 CH[n].TEP (n=0..19) 6.16.2.8 CHG[n] (n=0..5) 6.16.2.9 FORK[n].TEP (n=0..31) 6.17 PWM — Pulse width modulation 6.17.1 Wave counter 6.17.2 Decoder with EasyDMA 6.17.3 Limitations 6.17.4 Pin configuration 6.17.5 Registers 6.17.5.1 TASKS_STOP 6.17.5.2 TASKS_SEQSTART[n] (n=0..1) 6.17.5.3 TASKS_NEXTSTEP 6.17.5.4 EVENTS_STOPPED 6.17.5.5 EVENTS_SEQSTARTED[n] (n=0..1) 6.17.5.6 EVENTS_SEQEND[n] (n=0..1) 6.17.5.7 EVENTS_PWMPERIODEND 6.17.5.8 EVENTS_LOOPSDONE 6.17.5.9 SHORTS 6.17.5.10 INTEN 6.17.5.11 INTENSET 6.17.5.12 INTENCLR 6.17.5.13 ENABLE 6.17.5.14 MODE 6.17.5.15 COUNTERTOP 6.17.5.16 PRESCALER 6.17.5.17 DECODER 6.17.5.18 LOOP 6.17.5.19 SEQ[n].PTR (n=0..1) 6.17.5.20 SEQ[n].CNT (n=0..1) 6.17.5.21 SEQ[n].REFRESH (n=0..1) 6.17.5.22 SEQ[n].ENDDELAY (n=0..1) 6.17.5.23 PSEL.OUT[n] (n=0..3) 6.18 QDEC — Quadrature decoder 6.18.1 Sampling and decoding 6.18.2 LED output 6.18.3 Debounce filters 6.18.4 Accumulators 6.18.5 Output/input pins 6.18.6 Pin configuration 6.18.7 Registers 6.18.7.1 TASKS_START 6.18.7.2 TASKS_STOP 6.18.7.3 TASKS_READCLRACC 6.18.7.4 TASKS_RDCLRACC 6.18.7.5 TASKS_RDCLRDBL 6.18.7.6 EVENTS_SAMPLERDY 6.18.7.7 EVENTS_REPORTRDY 6.18.7.8 EVENTS_ACCOF 6.18.7.9 EVENTS_DBLRDY 6.18.7.10 EVENTS_STOPPED 6.18.7.11 SHORTS 6.18.7.12 INTENSET 6.18.7.13 INTENCLR 6.18.7.14 ENABLE 6.18.7.15 LEDPOL 6.18.7.16 SAMPLEPER 6.18.7.17 SAMPLE 6.18.7.18 REPORTPER 6.18.7.19 ACC 6.18.7.20 ACCREAD 6.18.7.21 PSEL.LED 6.18.7.22 PSEL.A 6.18.7.23 PSEL.B 6.18.7.24 DBFEN 6.18.7.25 LEDPRE 6.18.7.26 ACCDBL 6.18.7.27 ACCDBLREAD 6.18.8 Electrical specification 6.18.8.1 QDEC Electrical Specification 6.19 QSPI — Quad serial peripheral interface 6.19.1 Configuring peripheral 6.19.2 Write operation 6.19.3 Read operation 6.19.4 Erase operation 6.19.5 Execute in place 6.19.6 Sending custom instructions 6.19.6.1 Long frame mode 6.19.7 Deep power-down mode 6.19.8 Instruction set 6.19.9 Interface description 6.19.10 Registers 6.19.10.1 TASKS_ACTIVATE 6.19.10.2 TASKS_READSTART 6.19.10.3 TASKS_WRITESTART 6.19.10.4 TASKS_ERASESTART 6.19.10.5 TASKS_DEACTIVATE 6.19.10.6 EVENTS_READY 6.19.10.7 INTEN 6.19.10.8 INTENSET 6.19.10.9 INTENCLR 6.19.10.10 ENABLE 6.19.10.11 READ.SRC 6.19.10.12 READ.DST 6.19.10.13 READ.CNT 6.19.10.14 WRITE.DST 6.19.10.15 WRITE.SRC 6.19.10.16 WRITE.CNT 6.19.10.17 ERASE.PTR 6.19.10.18 ERASE.LEN 6.19.10.19 PSEL.SCK 6.19.10.20 PSEL.CSN 6.19.10.21 PSEL.IO0 6.19.10.22 PSEL.IO1 6.19.10.23 PSEL.IO2 6.19.10.24 PSEL.IO3 6.19.10.25 XIPOFFSET 6.19.10.26 IFCONFIG0 6.19.10.27 IFCONFIG1 6.19.10.28 STATUS 6.19.10.29 DPMDUR 6.19.10.30 ADDRCONF 6.19.10.31 CINSTRCONF 6.19.10.32 CINSTRDAT0 6.19.10.33 CINSTRDAT1 6.19.10.34 IFTIMING 6.19.11 Electrical specification 6.19.11.1 Timing specification 6.20 RADIO — 2.4 GHz radio 6.20.1 Packet configuration 6.20.2 Address configuration 6.20.3 Data whitening 6.20.4 CRC 6.20.5 Radio states 6.20.6 Transmit sequence 6.20.7 Receive sequence 6.20.8 Received signal strength indicator (RSSI) 6.20.9 Interframe spacing 6.20.10 Device address match 6.20.11 Bit counter 6.20.12 IEEE 802.15.4 operation 6.20.12.1 Packet structure 6.20.12.2 Operating frequencies 6.20.12.3 Energy detection (ED) 6.20.12.4 Clear channel assessment (CCA) 6.20.12.5 Cyclic redundancy check (CRC) 6.20.12.6 Transmit sequence 6.20.12.7 Receive sequence 6.20.12.8 Interframe spacing (IFS) 6.20.13 EasyDMA 6.20.14 Registers 6.20.14.1 TASKS_TXEN 6.20.14.2 TASKS_RXEN 6.20.14.3 TASKS_START 6.20.14.4 TASKS_STOP 6.20.14.5 TASKS_DISABLE 6.20.14.6 TASKS_RSSISTART 6.20.14.7 TASKS_RSSISTOP 6.20.14.8 TASKS_BCSTART 6.20.14.9 TASKS_BCSTOP 6.20.14.10 TASKS_EDSTART 6.20.14.11 TASKS_EDSTOP 6.20.14.12 TASKS_CCASTART 6.20.14.13 TASKS_CCASTOP 6.20.14.14 EVENTS_READY 6.20.14.15 EVENTS_ADDRESS 6.20.14.16 EVENTS_PAYLOAD 6.20.14.17 EVENTS_END 6.20.14.18 EVENTS_DISABLED 6.20.14.19 EVENTS_DEVMATCH 6.20.14.20 EVENTS_DEVMISS 6.20.14.21 EVENTS_RSSIEND 6.20.14.22 EVENTS_BCMATCH 6.20.14.23 EVENTS_CRCOK 6.20.14.24 EVENTS_CRCERROR 6.20.14.25 EVENTS_FRAMESTART 6.20.14.26 EVENTS_EDEND 6.20.14.27 EVENTS_EDSTOPPED 6.20.14.28 EVENTS_CCAIDLE 6.20.14.29 EVENTS_CCABUSY 6.20.14.30 EVENTS_CCASTOPPED 6.20.14.31 EVENTS_RATEBOOST 6.20.14.32 EVENTS_TXREADY 6.20.14.33 EVENTS_RXREADY 6.20.14.34 EVENTS_MHRMATCH 6.20.14.35 EVENTS_PHYEND 6.20.14.36 SHORTS 6.20.14.37 INTENSET 6.20.14.38 INTENCLR 6.20.14.39 CRCSTATUS 6.20.14.40 RXMATCH 6.20.14.41 RXCRC 6.20.14.42 DAI 6.20.14.43 PDUSTAT 6.20.14.44 PACKETPTR 6.20.14.45 FREQUENCY 6.20.14.46 TXPOWER 6.20.14.47 MODE 6.20.14.48 PCNF0 6.20.14.49 PCNF1 6.20.14.50 BASE0 6.20.14.51 BASE1 6.20.14.52 PREFIX0 6.20.14.53 PREFIX1 6.20.14.54 TXADDRESS 6.20.14.55 RXADDRESSES 6.20.14.56 CRCCNF 6.20.14.57 CRCPOLY 6.20.14.58 CRCINIT 6.20.14.59 TIFS 6.20.14.60 RSSISAMPLE 6.20.14.61 STATE 6.20.14.62 DATAWHITEIV 6.20.14.63 BCC 6.20.14.64 DAB[n] (n=0..7) 6.20.14.65 DAP[n] (n=0..7) 6.20.14.66 DACNF 6.20.14.67 MHRMATCHCONF 6.20.14.68 MHRMATCHMAS 6.20.14.69 MODECNF0 6.20.14.70 SFD 6.20.14.71 EDCNT 6.20.14.72 EDSAMPLE 6.20.14.73 CCACTRL 6.20.14.74 POWER 6.20.15 Electrical specification 6.20.15.1 General radio characteristics 6.20.15.2 Radio current consumption (transmitter) 6.20.15.3 Radio current consumption (Receiver) 6.20.15.4 Transmitter specification 6.20.15.5 Receiver operation 6.20.15.6 RX selectivity 6.20.15.7 RX intermodulation 6.20.15.8 Radio timing 6.20.15.9 Received signal strength indicator (RSSI) specifications 6.20.15.10 Jitter 6.20.15.11 IEEE 802.15.4 energy detection constants 6.21 RNG — Random number generator 6.21.1 Bias correction 6.21.2 Speed 6.21.3 Registers 6.21.3.1 TASKS_START 6.21.3.2 TASKS_STOP 6.21.3.3 EVENTS_VALRDY 6.21.3.4 SHORTS 6.21.3.5 INTENSET 6.21.3.6 INTENCLR 6.21.3.7 CONFIG 6.21.3.8 VALUE 6.21.4 Electrical specification 6.21.4.1 RNG Electrical Specification 6.22 RTC — Real-time counter 6.22.1 Clock source 6.22.2 Resolution versus overflow and the PRESCALER 6.22.3 COUNTER register 6.22.4 Overflow features 6.22.5 TICK event 6.22.6 Event control feature 6.22.7 Compare feature 6.22.8 TASK and EVENT jitter/delay 6.22.9 Reading the COUNTER register 6.22.10 Registers 6.22.10.1 TASKS_START 6.22.10.2 TASKS_STOP 6.22.10.3 TASKS_CLEAR 6.22.10.4 TASKS_TRIGOVRFLW 6.22.10.5 EVENTS_TICK 6.22.10.6 EVENTS_OVRFLW 6.22.10.7 EVENTS_COMPARE[n] (n=0..3) 6.22.10.8 INTENSET 6.22.10.9 INTENCLR 6.22.10.10 EVTEN 6.22.10.11 EVTENSET 6.22.10.12 EVTENCLR 6.22.10.13 COUNTER 6.22.10.14 PRESCALER 6.22.10.15 CC[n] (n=0..3) 6.22.11 Electrical specification 6.23 SAADC — Successive approximation analog-to-digital converter 6.23.1 Input configuration 6.23.1.1 Acquisition time 6.23.1.2 Internal resistor string (resistor ladder) 6.23.2 Reference voltage and gain settings 6.23.3 Digital output 6.23.4 EasyDMA 6.23.5 Continuous sampling 6.23.6 Oversampling 6.23.7 Event monitoring using limits 6.23.8 Calibration 6.23.9 Registers 6.23.9.1 TASKS_START 6.23.9.2 TASKS_SAMPLE 6.23.9.3 TASKS_STOP 6.23.9.4 TASKS_CALIBRATEOFFSET 6.23.9.5 EVENTS_STARTED 6.23.9.6 EVENTS_END 6.23.9.7 EVENTS_DONE 6.23.9.8 EVENTS_RESULTDONE 6.23.9.9 EVENTS_CALIBRATEDONE 6.23.9.10 EVENTS_STOPPED 6.23.9.11 EVENTS_CH[n].LIMITH (n=0..7) 6.23.9.12 EVENTS_CH[n].LIMITL (n=0..7) 6.23.9.13 INTEN 6.23.9.14 INTENSET 6.23.9.15 INTENCLR 6.23.9.16 STATUS 6.23.9.17 ENABLE 6.23.9.18 CH[n].PSELP (n=0..7) 6.23.9.19 CH[n].PSELN (n=0..7) 6.23.9.20 CH[n].CONFIG (n=0..7) 6.23.9.21 CH[n].LIMIT (n=0..7) 6.23.9.22 RESOLUTION 6.23.9.23 OVERSAMPLE 6.23.9.24 SAMPLERATE 6.23.9.25 RESULT.PTR 6.23.9.26 RESULT.MAXCNT 6.23.9.27 RESULT.AMOUNT 6.23.10 Electrical specification 6.23.10.1 SAADC electrical specification 6.24 SPI — Serial peripheral interface master 6.24.1 Functional description 6.24.1.1 SPI master mode pin configuration 6.24.1.2 Shared resources 6.24.1.3 SPI master transaction sequence 6.24.2 Registers 6.24.2.1 EVENTS_READY 6.24.2.2 INTENSET 6.24.2.3 INTENCLR 6.24.2.4 ENABLE 6.24.2.5 PSEL.SCK 6.24.2.6 PSEL.MOSI 6.24.2.7 PSEL.MISO 6.24.2.8 RXD 6.24.2.9 TXD 6.24.2.10 FREQUENCY 6.24.2.11 CONFIG 6.24.3 Electrical specification 6.24.3.1 SPI master interface electrical specifications 6.24.3.2 Serial Peripheral Interface (SPI) Master timing specifications 6.25 SPIM — Serial peripheral interface master with EasyDMA 6.25.1 SPI master transaction sequence 6.25.2 D/CX functionality 6.25.3 Pin configuration 6.25.4 EasyDMA 6.25.5 Low power 6.25.6 Registers 6.25.6.1 TASKS_START 6.25.6.2 TASKS_STOP 6.25.6.3 TASKS_SUSPEND 6.25.6.4 TASKS_RESUME 6.25.6.5 EVENTS_STOPPED 6.25.6.6 EVENTS_ENDRX 6.25.6.7 EVENTS_END 6.25.6.8 EVENTS_ENDTX 6.25.6.9 EVENTS_STARTED 6.25.6.10 SHORTS 6.25.6.11 INTENSET 6.25.6.12 INTENCLR 6.25.6.13 STALLSTAT 6.25.6.14 ENABLE 6.25.6.15 PSEL.SCK 6.25.6.16 PSEL.MOSI 6.25.6.17 PSEL.MISO 6.25.6.18 PSEL.CSN 6.25.6.19 FREQUENCY 6.25.6.20 RXD.PTR 6.25.6.21 RXD.MAXCNT 6.25.6.22 RXD.AMOUNT 6.25.6.23 RXD.LIST 6.25.6.24 TXD.PTR 6.25.6.25 TXD.MAXCNT 6.25.6.26 TXD.AMOUNT 6.25.6.27 TXD.LIST 6.25.6.28 CONFIG 6.25.6.29 IFTIMING.RXDELAY 6.25.6.30 IFTIMING.CSNDUR 6.25.6.31 CSNPOL 6.25.6.32 PSELDCX 6.25.6.33 DCXCNT 6.25.6.34 ORC 6.25.7 Electrical specification 6.25.7.1 Timing specifications 6.26 SPIS — Serial peripheral interface slave with EasyDMA 6.26.1 Shared resources 6.26.2 EasyDMA 6.26.3 SPI slave operation 6.26.4 Pin configuration 6.26.5 Registers 6.26.5.1 TASKS_ACQUIRE 6.26.5.2 TASKS_RELEASE 6.26.5.3 EVENTS_END 6.26.5.4 EVENTS_ENDRX 6.26.5.5 EVENTS_ACQUIRED 6.26.5.6 SHORTS 6.26.5.7 INTENSET 6.26.5.8 INTENCLR 6.26.5.9 SEMSTAT 6.26.5.10 STATUS 6.26.5.11 ENABLE 6.26.5.12 PSEL.SCK 6.26.5.13 PSEL.MISO 6.26.5.14 PSEL.MOSI 6.26.5.15 PSEL.CSN 6.26.5.16 PSELSCK ( Deprecated ) 6.26.5.17 PSELMISO ( Deprecated ) 6.26.5.18 PSELMOSI ( Deprecated ) 6.26.5.19 PSELCSN ( Deprecated ) 6.26.5.20 RXDPTR ( Deprecated ) 6.26.5.21 MAXRX ( Deprecated ) 6.26.5.22 AMOUNTRX ( Deprecated ) 6.26.5.23 RXD.PTR 6.26.5.24 RXD.MAXCNT 6.26.5.25 RXD.AMOUNT 6.26.5.26 RXD.LIST 6.26.5.27 TXDPTR ( Deprecated ) 6.26.5.28 MAXTX ( Deprecated ) 6.26.5.29 AMOUNTTX ( Deprecated ) 6.26.5.30 TXD.PTR 6.26.5.31 TXD.MAXCNT 6.26.5.32 TXD.AMOUNT 6.26.5.33 TXD.LIST 6.26.5.34 CONFIG 6.26.5.35 DEF 6.26.5.36 ORC 6.26.6 Electrical specification 6.26.6.1 SPIS slave interface electrical specifications 6.26.6.2 Serial Peripheral Interface Slave (SPIS) timing specifications 6.27 SWI — Software interrupts 6.27.1 Registers 6.28 TEMP — Temperature sensor 6.28.1 Registers 6.28.1.1 TASKS_START 6.28.1.2 TASKS_STOP 6.28.1.3 EVENTS_DATARDY 6.28.1.4 INTENSET 6.28.1.5 INTENCLR 6.28.1.6 TEMP 6.28.1.7 A0 6.28.1.8 A1 6.28.1.9 A2 6.28.1.10 A3 6.28.1.11 A4 6.28.1.12 A5 6.28.1.13 B0 6.28.1.14 B1 6.28.1.15 B2 6.28.1.16 B3 6.28.1.17 B4 6.28.1.18 B5 6.28.1.19 T0 6.28.1.20 T1 6.28.1.21 T2 6.28.1.22 T3 6.28.1.23 T4 6.28.2 Electrical specification 6.28.2.1 Temperature Sensor Electrical Specification 6.29 TWI — I2C compatible two-wire interface 6.29.1 Functional description 6.29.2 Master mode pin configuration 6.29.3 Shared resources 6.29.4 Master write sequence 6.29.5 Master read sequence 6.29.6 Master repeated start sequence 6.29.7 Low power 6.29.8 Registers 6.29.8.1 TASKS_STARTRX 6.29.8.2 TASKS_STARTTX 6.29.8.3 TASKS_STOP 6.29.8.4 TASKS_SUSPEND 6.29.8.5 TASKS_RESUME 6.29.8.6 EVENTS_STOPPED 6.29.8.7 EVENTS_RXDREADY 6.29.8.8 EVENTS_TXDSENT 6.29.8.9 EVENTS_ERROR 6.29.8.10 EVENTS_BB 6.29.8.11 EVENTS_SUSPENDED 6.29.8.12 SHORTS 6.29.8.13 INTENSET 6.29.8.14 INTENCLR 6.29.8.15 ERRORSRC 6.29.8.16 ENABLE 6.29.8.17 PSEL.SCL 6.29.8.18 PSEL.SDA 6.29.8.19 RXD 6.29.8.20 TXD 6.29.8.21 FREQUENCY 6.29.8.22 ADDRESS 6.29.9 Electrical specification 6.29.9.1 TWI interface electrical specifications 6.29.9.2 Two Wire Interface (TWI) timing specifications 6.30 TIMER — Timer/counter 6.30.1 Capture 6.30.2 Compare 6.30.3 Task delays 6.30.4 Task priority 6.30.5 Registers 6.30.5.1 TASKS_START 6.30.5.2 TASKS_STOP 6.30.5.3 TASKS_COUNT 6.30.5.4 TASKS_CLEAR 6.30.5.5 TASKS_SHUTDOWN ( Deprecated ) 6.30.5.6 TASKS_CAPTURE[n] (n=0..5) 6.30.5.7 EVENTS_COMPARE[n] (n=0..5) 6.30.5.8 SHORTS 6.30.5.9 INTENSET 6.30.5.10 INTENCLR 6.30.5.11 MODE 6.30.5.12 BITMODE 6.30.5.13 PRESCALER 6.30.5.14 CC[n] (n=0..5) 6.31 TWIM — I2C compatible two-wire interface master with EasyDMA 6.31.1 EasyDMA 6.31.2 Master write sequence 6.31.3 Master read sequence 6.31.4 Master repeated start sequence 6.31.5 Low power 6.31.6 Master mode pin configuration 6.31.7 Registers 6.31.7.1 TASKS_STARTRX 6.31.7.2 TASKS_STARTTX 6.31.7.3 TASKS_STOP 6.31.7.4 TASKS_SUSPEND 6.31.7.5 TASKS_RESUME 6.31.7.6 EVENTS_STOPPED 6.31.7.7 EVENTS_ERROR 6.31.7.8 EVENTS_SUSPENDED 6.31.7.9 EVENTS_RXSTARTED 6.31.7.10 EVENTS_TXSTARTED 6.31.7.11 EVENTS_LASTRX 6.31.7.12 EVENTS_LASTTX 6.31.7.13 SHORTS 6.31.7.14 INTEN 6.31.7.15 INTENSET 6.31.7.16 INTENCLR 6.31.7.17 ERRORSRC 6.31.7.18 ENABLE 6.31.7.19 PSEL.SCL 6.31.7.20 PSEL.SDA 6.31.7.21 FREQUENCY 6.31.7.22 RXD.PTR 6.31.7.23 RXD.MAXCNT 6.31.7.24 RXD.AMOUNT 6.31.7.25 RXD.LIST 6.31.7.26 TXD.PTR 6.31.7.27 TXD.MAXCNT 6.31.7.28 TXD.AMOUNT 6.31.7.29 TXD.LIST 6.31.7.30 ADDRESS 6.31.8 Electrical specification 6.31.8.1 TWIM interface electrical specifications 6.31.8.2 Two Wire Interface Master (TWIM) timing specifications 6.31.9 Pullup resistor 6.32 TWIS — I2C compatible two-wire interface slave with EasyDMA 6.32.1 EasyDMA 6.32.2 TWI slave responding to a read command 6.32.3 TWI slave responding to a write command 6.32.4 Master repeated start sequence 6.32.5 Terminating an ongoing TWI transaction 6.32.6 Low power 6.32.7 Slave mode pin configuration 6.32.8 Registers 6.32.8.1 TASKS_STOP 6.32.8.2 TASKS_SUSPEND 6.32.8.3 TASKS_RESUME 6.32.8.4 TASKS_PREPARERX 6.32.8.5 TASKS_PREPARETX 6.32.8.6 EVENTS_STOPPED 6.32.8.7 EVENTS_ERROR 6.32.8.8 EVENTS_RXSTARTED 6.32.8.9 EVENTS_TXSTARTED 6.32.8.10 EVENTS_WRITE 6.32.8.11 EVENTS_READ 6.32.8.12 SHORTS 6.32.8.13 INTEN 6.32.8.14 INTENSET 6.32.8.15 INTENCLR 6.32.8.16 ERRORSRC 6.32.8.17 MATCH 6.32.8.18 ENABLE 6.32.8.19 PSEL.SCL 6.32.8.20 PSEL.SDA 6.32.8.21 RXD.PTR 6.32.8.22 RXD.MAXCNT 6.32.8.23 RXD.AMOUNT 6.32.8.24 RXD.LIST 6.32.8.25 TXD.PTR 6.32.8.26 TXD.MAXCNT 6.32.8.27 TXD.AMOUNT 6.32.8.28 TXD.LIST 6.32.8.29 ADDRESS[n] (n=0..1) 6.32.8.30 CONFIG 6.32.8.31 ORC 6.32.9 Electrical specification 6.32.9.1 TWIS slave timing specifications 6.33 UART — Universal asynchronous receiver/transmitter 6.33.1 Functional description 6.33.2 Pin configuration 6.33.3 Shared resources 6.33.4 Transmission 6.33.5 Reception 6.33.6 Suspending the UART 6.33.7 Error conditions 6.33.8 Using the UART without flow control 6.33.9 Parity and stop bit configuration 6.33.10 Registers 6.33.10.1 TASKS_STARTRX 6.33.10.2 TASKS_STOPRX 6.33.10.3 TASKS_STARTTX 6.33.10.4 TASKS_STOPTX 6.33.10.5 TASKS_SUSPEND 6.33.10.6 EVENTS_CTS 6.33.10.7 EVENTS_NCTS 6.33.10.8 EVENTS_RXDRDY 6.33.10.9 EVENTS_TXDRDY 6.33.10.10 EVENTS_ERROR 6.33.10.11 EVENTS_RXTO 6.33.10.12 SHORTS 6.33.10.13 INTENSET 6.33.10.14 INTENCLR 6.33.10.15 ERRORSRC 6.33.10.16 ENABLE 6.33.10.17 PSEL.RTS 6.33.10.18 PSEL.TXD 6.33.10.19 PSEL.CTS 6.33.10.20 PSEL.RXD 6.33.10.21 RXD 6.33.10.22 TXD 6.33.10.23 BAUDRATE 6.33.10.24 CONFIG 6.33.11 Electrical specification 6.33.11.1 UART electrical specification 6.34 UARTE — Universal asynchronous receiver/transmitter with EasyDMA 6.34.1 EasyDMA 6.34.2 Transmission 6.34.3 Reception 6.34.4 Error conditions 6.34.5 Using the UARTE without flow control 6.34.6 Parity and stop bit configuration 6.34.7 Low power 6.34.8 Pin configuration 6.34.9 Registers 6.34.9.1 TASKS_STARTRX 6.34.9.2 TASKS_STOPRX 6.34.9.3 TASKS_STARTTX 6.34.9.4 TASKS_STOPTX 6.34.9.5 TASKS_FLUSHRX 6.34.9.6 EVENTS_CTS 6.34.9.7 EVENTS_NCTS 6.34.9.8 EVENTS_RXDRDY 6.34.9.9 EVENTS_ENDRX 6.34.9.10 EVENTS_TXDRDY 6.34.9.11 EVENTS_ENDTX 6.34.9.12 EVENTS_ERROR 6.34.9.13 EVENTS_RXTO 6.34.9.14 EVENTS_RXSTARTED 6.34.9.15 EVENTS_TXSTARTED 6.34.9.16 EVENTS_TXSTOPPED 6.34.9.17 SHORTS 6.34.9.18 INTEN 6.34.9.19 INTENSET 6.34.9.20 INTENCLR 6.34.9.21 ERRORSRC 6.34.9.22 ENABLE 6.34.9.23 PSEL.RTS 6.34.9.24 PSEL.TXD 6.34.9.25 PSEL.CTS 6.34.9.26 PSEL.RXD 6.34.9.27 BAUDRATE 6.34.9.28 RXD.PTR 6.34.9.29 RXD.MAXCNT 6.34.9.30 RXD.AMOUNT 6.34.9.31 TXD.PTR 6.34.9.32 TXD.MAXCNT 6.34.9.33 TXD.AMOUNT 6.34.9.34 CONFIG 6.34.10 Electrical specification 6.34.10.1 UARTE electrical specification 6.35 USBD — Universal serial bus device 6.35.1 USB device states 6.35.2 USB terminology 6.35.3 USB pins 6.35.4 USBD power-up sequence 6.35.5 USB pull-up 6.35.6 USB reset 6.35.7 USB suspend and resume 6.35.7.1 Entering suspend 6.35.7.2 Host-initiated resume 6.35.7.3 Device-initiated remote wake-up 6.35.8 EasyDMA 6.35.9 Control transfers 6.35.9.1 Control read transfer 6.35.9.2 Control write transfer 6.35.10 Bulk and interrupt transactions 6.35.10.1 Bulk and interrupt IN transaction 6.35.10.2 Bulk and interrupt OUT transaction 6.35.11 Isochronous transactions 6.35.11.1 Isochronous IN transaction 6.35.11.2 Isochronous OUT transaction 6.35.12 USB register access limitations 6.35.13 Registers 6.35.13.1 TASKS_STARTEPIN[n] (n=0..7) 6.35.13.2 TASKS_STARTISOIN 6.35.13.3 TASKS_STARTEPOUT[n] (n=0..7) 6.35.13.4 TASKS_STARTISOOUT 6.35.13.5 TASKS_EP0RCVOUT 6.35.13.6 TASKS_EP0STATUS 6.35.13.7 TASKS_EP0STALL 6.35.13.8 TASKS_DPDMDRIVE 6.35.13.9 TASKS_DPDMNODRIVE 6.35.13.10 EVENTS_USBRESET 6.35.13.11 EVENTS_STARTED 6.35.13.12 EVENTS_ENDEPIN[n] (n=0..7) 6.35.13.13 EVENTS_EP0DATADONE 6.35.13.14 EVENTS_ENDISOIN 6.35.13.15 EVENTS_ENDEPOUT[n] (n=0..7) 6.35.13.16 EVENTS_ENDISOOUT 6.35.13.17 EVENTS_SOF 6.35.13.18 EVENTS_USBEVENT 6.35.13.19 EVENTS_EP0SETUP 6.35.13.20 EVENTS_EPDATA 6.35.13.21 SHORTS 6.35.13.22 INTEN 6.35.13.23 INTENSET 6.35.13.24 INTENCLR 6.35.13.25 EVENTCAUSE 6.35.13.26 HALTED.EPIN[n] (n=0..7) 6.35.13.27 HALTED.EPOUT[n] (n=0..7) 6.35.13.28 EPSTATUS 6.35.13.29 EPDATASTATUS 6.35.13.30 USBADDR 6.35.13.31 BMREQUESTTYPE 6.35.13.32 BREQUEST 6.35.13.33 WVALUEL 6.35.13.34 WVALUEH 6.35.13.35 WINDEXL 6.35.13.36 WINDEXH 6.35.13.37 WLENGTHL 6.35.13.38 WLENGTHH 6.35.13.39 SIZE.EPOUT[n] (n=0..7) 6.35.13.40 SIZE.ISOOUT 6.35.13.41 ENABLE 6.35.13.42 USBPULLUP 6.35.13.43 DPDMVALUE 6.35.13.44 DTOGGLE 6.35.13.45 EPINEN 6.35.13.46 EPOUTEN 6.35.13.47 EPSTALL 6.35.13.48 ISOSPLIT 6.35.13.49 FRAMECNTR 6.35.13.50 LOWPOWER 6.35.13.51 ISOINCONFIG 6.35.13.52 EPIN[n].PTR (n=0..7) 6.35.13.53 EPIN[n].MAXCNT (n=0..7) 6.35.13.54 EPIN[n].AMOUNT (n=0..7) 6.35.13.55 ISOIN.PTR 6.35.13.56 ISOIN.MAXCNT 6.35.13.57 ISOIN.AMOUNT 6.35.13.58 EPOUT[n].PTR (n=0..7) 6.35.13.59 EPOUT[n].MAXCNT (n=0..7) 6.35.13.60 EPOUT[n].AMOUNT (n=0..7) 6.35.13.61 ISOOUT.PTR 6.35.13.62 ISOOUT.MAXCNT 6.35.13.63 ISOOUT.AMOUNT 6.35.14 Electrical specification 6.35.14.1 USB Electrical Specification 6.36 WDT — Watchdog timer 6.36.1 Reload criteria 6.36.2 Temporarily pausing the watchdog 6.36.3 Watchdog reset 6.36.4 Registers 6.36.4.1 TASKS_START 6.36.4.2 EVENTS_TIMEOUT 6.36.4.3 INTENSET 6.36.4.4 INTENCLR 6.36.4.5 RUNSTATUS 6.36.4.6 REQSTATUS 6.36.4.7 CRV 6.36.4.8 RREN 6.36.4.9 CONFIG 6.36.4.10 RR[n] (n=0..7) 6.36.5 Electrical specification 6.36.5.1 Watchdog Timer Electrical Specification Hardware and layout 7.1 Pin assignments 7.1.1 aQFN73 ball assignments 7.1.2 WLCSP ball assignments 7.2 Mechanical specifications 7.2.1 aQFN73 7 x 7 mm package 7.2.2 WLCSP 3.544 x 3.607 mm package 7.3 Reference circuitry 7.3.1 Circuit configuration no. 1 7.3.2 Circuit configuration no. 2 7.3.3 Circuit configuration no. 3 7.3.4 Circuit configuration no. 4 7.3.5 Circuit configuration no. 5 7.3.6 Circuit configuration no. 6 7.3.7 Circuit configuration no. 1 for CKAA WLCSP 7.3.8 Circuit configuration no. 2 for CKAA WLCSP 7.3.9 Circuit configuration no. 3 for CKAA WLCSP 7.3.10 Circuit configuration no. 4 for CKAA WLCSP 7.3.11 Circuit configuration no. 5 for CKAA WLCSP 7.3.12 Circuit configuration no. 6 for CKAA WLCSP 7.3.13 PCB guidelines 7.3.14 PCB layout example Recommended operating conditions Absolute maximum ratings Ordering information 10.1 Package marking 10.2 Box labels 10.3 Order code 10.4 Code ranges and values 10.5 Product options Legal notices 11.1 Liability disclaimer 11.2 Life support applications 11.3 RoHS and REACH statement 11.4 Trademarks 11.5 Copyright notice