Datasheet ADCMP608 (Analog Devices) - 7

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Data Sheet ADCMP608 APPLICATIONS INFORMATION POWER/GROUND LAYOUT AND BYPASSING VLOGIC
The ADCMP608 comparator is a high speed device. Despite the low noise output stage, it is essential to use proper high speed
A1 Q1
design techniques to achieve the specified performance. Because comparators are uncompensated amplifiers, feedback in any phase relationship is likely to cause oscillations or undesired hysteresis. Of
+IN OUTPUT
critical importance is the use of low impedance supply planes,
AV –IN
particularly the output supply plane (VCC) and the ground plane (GND). Individual supply planes are recommended as part of a multilayer board. Providing the lowest inductance return path for
A2 Q2
switching currents ensures the best possible performance in the target application. 09 0
GAIN STAGE OUTPUT STAGE
9- 76 It is also important to adequately bypass the input and output 06 supplies. A 0.1 μF bypass capacitor should be placed as close as Figure 9. Simplified Schematic Diagram of TTL-/CMOS-Compatible Output Stage possible to the VCC supply pin. The capacitor should be connected to the GND plane with redundant vias placed to provide a
OPTIMIZING PERFORMANCE
physically short return path for output currents flowing back As with any high speed comparator, proper design and layout from ground to the VCC pin. High frequency bypass capacitors techniques are essential for obtaining the specified performance. should be carefully selected for minimum inductance and ESR. Stray capacitance, inductance, common power and ground Parasitic layout inductance should also be strictly controlled to impedances, or other layout issues can severely limit performance maximize the effectiveness of the bypass at high frequencies. and can often cause oscillation. The source impedance should be
TTL-/CMOS-COMPATIBLE OUTPUT STAGE
minimized as much as is practicable. High source impedance, in combination with the parasitic input capacitance of the comparator, Specified propagation delay performance can be achieved only causes an undesirable degradation in bandwidth at the input, thus by keeping the capacitive load at or below the specified minimums. degrading the overall response. Higher impedances encourage The output of the ADCMP608 is designed to directly drive one undesired coupling. Schottky TTL, or three low power Schottky TTL loads, or the equivalent. For large fan outs, buses, or transmission lines, use
COMPARATOR PROPAGATION DELAY DISPERSION
an appropriate buffer to maintain the excellent speed and The ADCMP608 comparator is designed to reduce propagation stability of the comparator. delay dispersion over a wide input overdrive range of 10 mV to With the rated 15 pF load capacitance applied, more than half VCC – 1 V. Propagation delay dispersion is the variation in of the total device propagation delay is output stage slew time. propagation delay that results from a change in the degree of Because of this, the total propagation delay decreases as V overdrive or slew rate (how far or how fast the input signal CC decreases, and instability in the power supply may appear as exceeds the switching threshold). excess delay dispersion. Propagation delay dispersion is a specification that becomes Delay is measured to the 50% point for whatever supply is in important in high speed, time-critical applications, such as data use; thus, the fastest times are observed with the V communication, automatic test and measurement, and instru- CC supply at 2.5 V, and larger values are observed when driving loads that mentation. It is also important in event-driven applications, such switch at other levels. as pulse spectroscopy, nuclear instrumentation, and medical imaging. Dispersion is defined as the variation in propagation Overdrive and input slew rate dispersions are not significantly delay as the input overdrive conditions are changed (see Figure 10 affected by output loading and VCC variations. and Figure 11). The TTL-/CMOS-compatible output stage is shown in the ADCMP608 dispersion is typically < 12 ns as the overdrive simplified schematic diagram (see Figure 9). Because of its varies from 10 mV to 125 mV. This specification applies to both inherent symmetry and generally good behavior, this output positive and negative signals because the device has very closely stage is readily adaptable for driving various filters and other matched delays for both positive-going and negative-going unusual loads. inputs, and very low output skews. Remember to add the actual device offset to the overdrive for repeatable dispersion measurements. Rev. B | Page 7 of 10 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ELECTRICAL CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS APPLICATIONS INFORMATION POWER/GROUND LAYOUT AND BYPASSING TTL-/CMOS-COMPATIBLE OUTPUT STAGE OPTIMIZING PERFORMANCE COMPARATOR PROPAGATION DELAY DISPERSION CROSSOVER BIAS POINT MINIMUM INPUT SLEW RATE REQUIREMENT TYPICAL APPLICATION CIRCUITS OUTLINE DIMENSIONS ORDERING GUIDE