Datasheet ADCMP603 (Analog Devices) - 8
Manufacturer | Analog Devices |
Description | Rail-to-Rail, Very Fast, 2.5 V to 5.5 V, Single-Supply TTL/CMOS Comparator |
Pages / Page | 16 / 8 — ADCMP603. Data Sheet. TYPICAL PERFORMANCE CHARACTERISTICS. 800. 600. CC = … |
Revision | A |
File Format / Size | PDF / 321 Kb |
Document Language | English |
ADCMP603. Data Sheet. TYPICAL PERFORMANCE CHARACTERISTICS. 800. 600. CC = 2.5V. CC = 5.5V. V (. 400. 200. OLTA. T V. –200. CURRE. L OU
Model Line for this Datasheet
Text Version of Document
ADCMP603 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS
VCCI = VCCO = 2.5 V, TA = 25°C, unless otherwise noted.
800 4 600 V V ) 3 CC = 2.5V CC = 5.5V V ( 400 GE 2 A) 200 µ OLTA ( T V NT 0 U 1 TP –200 CURRE L OU 0 A OUTPUT VOLTAGE IC –400 P TY –1 –600
007 010
–800
05915-
–2
05915-
–1 0 1 2 3 4 5 6 7 –5 0 5 10 15 20 LE/HYSTERESIS PIN VOLTAGE (V) LOAD CURRENT (mA)
Figure 4. LE/HYS Pin I/V Curve Figure 7. VOL vs. Load Current
200 1000 150 V 100 CC = 5.5V VCC = 2.5V V) 100 A) µ VCC = 5.5V ( 50 S (m NT ESI 0 ER VCC = 2.5V CURRE YST H 10 –50 –100
006 004 05915-
–150
05915-
1 –1 0 1 2 3 4 5 6 7 50 150 250 350 450 550 650 SHUTDOWN PIN VOLTAGE (V) HYSTERESIS RESISTOR (kΩ)
Figure 5. SDN Pin I/V Curve Figure 8. Hysteresis vs. RHYS
20 350 V I CC = 2.5V B @ +125°C 15 300 IB @ +25°C HYSTERESIS @ +125°C 10 IB @ –40°C 250 V) 5 S (m 200 A) µ ( 0 ESI HYSTERESIS @ +25°C I B ER 150 –5 YST H 100 –10 –15 50
005 003
HYSTERESIS @ –40°C
05915-
–20
05915-
0 –1.0 –0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 0 –2 –4 –6 –8 –10 –12 –14 –16 –18 COMMON-MODE VOLTAGE (V) HYSTERESIS PIN CURRENT (µA)
Figure 6. Input Bias Current vs. Input Common Mode Figure 9. Hysteresis vs. Hysteresis Pin Current Rev. A | Page 8 of 16 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ELECTRICAL CHARACTERISTICS TIMING INFORMATION ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS APPLICATIONS INFORMATION POWER/GROUND LAYOUT AND BYPASSING TTL-/CMOS-COMPATIBLE OUTPUT STAGE USING/DISABLING THE LATCH FEATURE OPTIMIZING PERFORMANCE COMPARATOR PROPAGATION DELAY DISPERSION COMPARATOR HYSTERESIS CROSSOVER BIAS POINT MINIMUM INPUT SLEW RATE REQUIREMENT TYPICAL APPLICATION CIRCUITS OUTLINE DIMENSIONS ORDERING GUIDE