Datasheet ADCMP566 (Analog Devices) - 6

ADCMP566 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
D D D GN LEA LEA NC GN QA QA GN 32 31 30 29 28 27 26 25 GND 1 PIN 1 24 VEE –INA 2 INDICATOR 23 NC +INA 3 22 VEE V 4 ADCMP566 21 V CC CC V 5 20 V CC TOP VIEW CC +INB 6 19 VEE (Not to Scale) –INB 7 18 NC GND 8 17 VEE 9 0 1 2 3 6 1 1 1 1 14 15 1 NC QB QB GND LEB LEB GND GND NC = NO CONNECT 03633-0-002
Figure 2. ADCMP566 Pin Configuration
Table 3. ADCMP566 Pin Descriptions Pin No. Mnemonic Function
1 GND Analog Ground 2 −INA Inverting analog input of the differential input stage for Channel A. The inverting A input must be driven in conjunction with the noninverting A input. 3 +INA Noninverting analog input of the differential input stage for Channel A. The noninverting A input must be driven in conjunction with the inverting A input. 4 VCC Positive Supply Terminal 5 VCC Positive Supply Terminal 6 +INB Noninverting analog input of the differential input stage for Channel B. The noninverting B input must be driven in conjunction with the inverting B input. 7 −INB Inverting analog input of the differential input stage for Channel B. The inverting B input must be driven in conjunction with the noninverting B input. 8 GND Analog Ground 9 GND Analog Ground 10 LEB One of two complementary inputs for Channel B Latch Enable. In the compare mode (logic low), the output will track changes at the input of the comparator. In the latch mode (logic high), the output will reflect the input state just prior to the comparator’s being placed in the latch mode. LEB must be driven in conjunction with LEB. 11 LEB One of two complementary inputs for Channel B Latch Enable. In the compare mode (logic high), the output will track changes at the input of the comparator. In the latch mode (logic low), the output will reflect the input state just prior to the comparator’s being placed in the latch mode. LEB must be driven in conjunction with LEB. 12 NC No Connect. Leave pin unconnected. 13 GND Digital Ground 14 QB One of two complementary outputs for Channel B. QB will be at logic low if the analog voltage at the noninverting input is greater than the analog voltage at the inverting input (provided the comparator is in the compare mode). See the LEB description (Pin 11) for more information. 15 QB One of two complementary outputs for Channel B. QB will be at logic high if the analog voltage at the noninverting input is greater than the analog voltage at the inverting input (provided the comparator is in the compare mode). See the LEB description (Pin 11) for more information. 16 GND Digital Ground 17 VEE Negative Supply Terminal 18 NC No Connect. Leave pin unconnected. 19 VEE Negative Supply Terminal 20 VCC Positive Supply Terminal 21 VCC Positive Supply Terminal Rev. 0 | Page 6 of 16 Document Outline SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL CONSIDERATIONS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TIMING INFORMATION APPLICATION INFORMATION CLOCK TIMING RECOVERY OPTIMIZING HIGH SPEED PERFORMANCE COMPARATOR PROPAGATION DELAY DISPERSION COMPARATOR HYSTERESIS MINIMUM INPUT SLEW RATE REQUIREMENT TYPICAL APPLICATION CIRCUITS TYPICAL PERFORMANCE CHARACTERISTICS OUTLINE DIMENSIONS ORDERING GUIDE