Datasheet LT3072 (Analog Devices) - 15
| Manufacturer | Analog Devices |
| Description | Dual, Low Noise, 2.5A Programmable Output, 80mV Low Dropout Linear Regulator |
| Pages / Page | 28 / 15 — BLOCK DIAGRAM |
| File Format / Size | PDF / 2.5 Mb |
| Document Language | English |
BLOCK DIAGRAM
Model Line for this Datasheet
Text Version of Document
LT3072
BLOCK DIAGRAM
INn BIAS LDO BUF OUT-over-IN ENn PWRGDn VIOCn DETECTION 2V INTERNAL + SUPPLY 8k IMON/LIMn CURRENT REV_DETECT MONITOR I – OUTn g I m = 16.7m MON = 3000 160k I 3000 LIM = – – 20mΩ OUTn RMON EXTERNAL INTERNAL 240k ILIMIT ILIMIT + + 66mV 32k 2V + – CHOPPER CH_EN STABILIZED n ERROR 66.7µA AMP REF/BYPn HIREFn (1.2V) OUTn ≥ 1.2V + EN – REFn 4k SENSEn 81k 10.1k MARGAn LOREFn (0.6V) IDEAL 60k OUTn ≥ 1.15V DIODE 81k 10.1k 0.55V + CH_ENn BIAS_UVLO VIOCn EN VIOC INT_ENn – – + 0.85V INT_ENn INn–BIAS_OVLO – + ENn + 0.2V INn – + – I 0.45V = OUTn TEMP 12µA FOR ENn > 1.8V BIAS_UVLO + 2.15V 16.67A MONITOR TEMP 150k FOR ENn < 1.8V – BIAS 10mV/°C 25°C = 250mV INn_UVLO + 0.5V – INn + TLIMIT TLIMIT PWRGDn REV_DETECT – 1.68V – 35µs DELAY 3.692k ON SENSEn + 93.5% TO ∞ FALLING EDGE REFn OUTPUT VOLTAGE SELECTION 5% HYST VOnB2 V V GND OnB1 OnB0 OUTPUT VOLTAGE SELECTION TRI-STATE LOGIC PINS BIAS 1.1V 90mV HYST – 0.86V 80k FOR VOnBx < 1.1V LOGIC-1 STATE ∞ FOR V + OnBx > 1.1V VOnB2, VOnB1, VOnB0 LOGIC-Z STATE 120k FOR V – OnBx < 2V 16.7µA FOR VOnBx > 2V LOGIC-0 STATE + 0.33V 65mV HYST 3072 BD02 Rev. 0 For more information www.analog.com 15 Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Applications Information Typical Applications Package Description Typical Application Related Parts
BLOCK DIAGRAM
INn BIAS LDO BUF OUT-over-IN ENn PWRGDn VIOCn DETECTION 2V INTERNAL + SUPPLY 8k IMON/LIMn CURRENT REV_DETECT MONITOR I – OUTn g I m = 16.7m MON = 3000 160k I 3000 LIM = – – 20mΩ OUTn RMON EXTERNAL INTERNAL 240k ILIMIT ILIMIT + + 66mV 32k 2V + – CHOPPER CH_EN STABILIZED n ERROR 66.7µA AMP REF/BYPn HIREFn (1.2V) OUTn ≥ 1.2V + EN – REFn 4k SENSEn 81k 10.1k MARGAn LOREFn (0.6V) IDEAL 60k OUTn ≥ 1.15V DIODE 81k 10.1k 0.55V + CH_ENn BIAS_UVLO VIOCn EN VIOC INT_ENn – – + 0.85V INT_ENn INn–BIAS_OVLO – + ENn + 0.2V INn – + – I 0.45V = OUTn TEMP 12µA FOR ENn > 1.8V BIAS_UVLO + 2.15V 16.67A MONITOR TEMP 150k FOR ENn < 1.8V – BIAS 10mV/°C 25°C = 250mV INn_UVLO + 0.5V – INn + TLIMIT TLIMIT PWRGDn REV_DETECT – 1.68V – 35µs DELAY 3.692k ON SENSEn + 93.5% TO ∞ FALLING EDGE REFn OUTPUT VOLTAGE SELECTION 5% HYST VOnB2 V V GND OnB1 OnB0 OUTPUT VOLTAGE SELECTION TRI-STATE LOGIC PINS BIAS 1.1V 90mV HYST – 0.86V 80k FOR VOnBx < 1.1V LOGIC-1 STATE ∞ FOR V + OnBx > 1.1V VOnB2, VOnB1, VOnB0 LOGIC-Z STATE 120k FOR V – OnBx < 2V 16.7µA FOR VOnBx > 2V LOGIC-0 STATE + 0.33V 65mV HYST 3072 BD02 Rev. 0 For more information www.analog.com 15 Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Applications Information Typical Applications Package Description Typical Application Related Parts
