Datasheet ADP7142 (Analog Devices) - 6
| Manufacturer | Analog Devices |
| Description | 40 V, 200 mA, Low Noise, CMOS LDO Linear Regulator |
| Pages / Page | 23 / 6 — ADP7142. Data Sheet. PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS. VOUT … |
| Revision | H |
| File Format / Size | PDF / 1.1 Mb |
| Document Language | English |
ADP7142. Data Sheet. PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS. VOUT 1. 6 VIN. 8 VIN. SENSE/ADJ 2. TOP VIEW. 5 SS. VOUT 2. 7 VIN
Model Line for this Datasheet
- ADP7142ACPZN-R7 ADP7142ACPZN1.8-R7 ADP7142ACPZN2.5-R7 ADP7142ACPZN3.3-R7 ADP7142ACPZN3.8-R7 ADP7142ACPZN5.0-R7 ADP7142ARDZ ADP7142ARDZ-1.8 ADP7142ARDZ-1.8-R7 ADP7142ARDZ-2.5 ADP7142ARDZ-2.5-R7 ADP7142ARDZ-3.3 ADP7142ARDZ-3.3-R7 ADP7142ARDZ-5.0 ADP7142ARDZ-5.0-R7 ADP7142ARDZ-R7 ADP7142AUJZ-1.8-R7 ADP7142AUJZ-2.5-R7 ADP7142AUJZ-3.3-R7 ADP7142AUJZ-5.0-R7 ADP7142AUJZ-R2 ADP7142AUJZ-R7 ADP7142WAUJZ-1.8-R7 ADP7142WAUJZ-2.5-R7 ADP7142WAUJZ-3.3-R7 ADP7142WAUJZ-5.0-R7 ADP7142WAUJZ-R7
Text Version of Document
ADP7142 Data Sheet PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS VOUT 1 6 VIN ADP7142 VOUT 1 8 VIN SENSE/ADJ 2 TOP VIEW 5 SS VOUT 2 ADP7142 7 VIN (Not to Scale) TOP VIEW SENSE/ADJ 3 (Not to Scale) 6 SS GND 3 EXPOSED PAD 4 EN GND 4 5 EN NOTES NOTES 1. THE EXPOSED PAD ON THE BOTTOM OF THE PACKAGE 1. THE EXPOSED PAD ON THE BOTTOM OF THE PACKAGE ENHANCES THERMAL PERFORMANCE AND IS ENHANCES THERMAL PERFORMANCE AND IS ELECTRICALLY CONNECTED TO GND INSIDE THE
3
ELECTRICALLY CONNECTED TO GND INSIDE THE
00 105
PACKAGE. IT IS RECOMMENDED THAT THE EXPOSED
8-
PACKAGE. IT IS RECOMMENDED THAT THE EXPOSED PAD CONNECT TO THE GROUND PLANE ON THE BOARD. PAD CONNECT TO THE GROUND PLANE ON THE BOARD.
1184 11848- Figure 3. 6-Lead LFCSP Pin Configuration Figure 5. 8-Lead SOIC Pin Configuration
VIN 1 5 VOUT ADP7142 GND 2 TOP VIEW (Not to Scale)
-104
EN 3 4 SENSE/ADJ
11848 Figure 4. 5-Lead TSOT Pin Configuration
Table 5. Pin Function Descriptions Pin No. 6-Lead 8-Lead 5-Lead LFCSP SOIC TSOT Mnemonic Description
1 1, 2 5 VOUT Regulated Output Voltage. Bypass VOUT to GND with a 2.2 μF or greater capacitor. 2 3 4 SENSE/ADJ Sense Input (SENSE). Connect to load. An external resistor divider may also be used to set the output voltage higher than the fixed output voltage (ADJ). 3 4 2 GND Ground. 4 5 3 EN The enable pin controls the operation of the LDO. Drive EN high to turn on the regulator. Drive EN low to turn off the regulator. For automatic startup, connect EN to VIN. 5 6 Not SS Soft Start. An external capacitor connected to this pin determines the soft-start applicable time. Leave this pin open for a typical 380 μs start-up time. Do not ground this pin. 6 7, 8 1 VIN Regulator Input Supply. Bypass VIN to GND with a 2.2 μF or greater capacitor. EP Exposed Pad. The exposed pad on the bottom of the package enhances thermal performance and is electrically connected to GND inside the package. It is recommended that the exposed pad connect to the ground plane on the board. Rev. H | Page 6 of 23 Document Outline Features Applications Typical Application Circuits General Description Revision History Specifications Input and Output Capacitance, Recommended Specifications Absolute Maximum Ratings Thermal Data Thermal Resistance ESD Caution Pin Configurations and Function Descriptions Typical Performance Characteristics Theory of Operation Applications Information ADIsimPower Design Tool Capacitor Selection Output Capacitor Input Bypass Capacitor Input and Output Capacitor Properties Programable Precision Enable Soft Start Noise Reduction of the ADP7142 in Adjustable Mode Effect of Noise Reduction on Start-Up Time Current-Limit and Thermal Overload Protection Thermal Considerations Printed Circuit Board Layout Considerations Outline Dimensions Ordering Guide
3
ELECTRICALLY CONNECTED TO GND INSIDE THE
00 105
PACKAGE. IT IS RECOMMENDED THAT THE EXPOSED
8-
PACKAGE. IT IS RECOMMENDED THAT THE EXPOSED PAD CONNECT TO THE GROUND PLANE ON THE BOARD. PAD CONNECT TO THE GROUND PLANE ON THE BOARD.
1184 11848- Figure 3. 6-Lead LFCSP Pin Configuration Figure 5. 8-Lead SOIC Pin Configuration
VIN 1 5 VOUT ADP7142 GND 2 TOP VIEW (Not to Scale)
-104
EN 3 4 SENSE/ADJ
11848 Figure 4. 5-Lead TSOT Pin Configuration
Table 5. Pin Function Descriptions Pin No. 6-Lead 8-Lead 5-Lead LFCSP SOIC TSOT Mnemonic Description
1 1, 2 5 VOUT Regulated Output Voltage. Bypass VOUT to GND with a 2.2 μF or greater capacitor. 2 3 4 SENSE/ADJ Sense Input (SENSE). Connect to load. An external resistor divider may also be used to set the output voltage higher than the fixed output voltage (ADJ). 3 4 2 GND Ground. 4 5 3 EN The enable pin controls the operation of the LDO. Drive EN high to turn on the regulator. Drive EN low to turn off the regulator. For automatic startup, connect EN to VIN. 5 6 Not SS Soft Start. An external capacitor connected to this pin determines the soft-start applicable time. Leave this pin open for a typical 380 μs start-up time. Do not ground this pin. 6 7, 8 1 VIN Regulator Input Supply. Bypass VIN to GND with a 2.2 μF or greater capacitor. EP Exposed Pad. The exposed pad on the bottom of the package enhances thermal performance and is electrically connected to GND inside the package. It is recommended that the exposed pad connect to the ground plane on the board. Rev. H | Page 6 of 23 Document Outline Features Applications Typical Application Circuits General Description Revision History Specifications Input and Output Capacitance, Recommended Specifications Absolute Maximum Ratings Thermal Data Thermal Resistance ESD Caution Pin Configurations and Function Descriptions Typical Performance Characteristics Theory of Operation Applications Information ADIsimPower Design Tool Capacitor Selection Output Capacitor Input Bypass Capacitor Input and Output Capacitor Properties Programable Precision Enable Soft Start Noise Reduction of the ADP7142 in Adjustable Mode Effect of Noise Reduction on Start-Up Time Current-Limit and Thermal Overload Protection Thermal Considerations Printed Circuit Board Layout Considerations Outline Dimensions Ordering Guide
