Datasheet ADM7155 (Analog Devices) - 6

ADM7155 Data Sheet PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS VREG 1 8 VIN VREG 1 8 VIN VOUT 2 ADM7155 7 EN VOUT 2 7 EN ADM7155 TOP VIEW BYP 3 (Not to Scale) 6 REF BYP 3 TOP VIEW 6 REF (Not to Scale) GND 4 5 REF_SENSE GND 4 5 REF_SENSE NOTES NOTES 1. THE EXPOSED PAD IS LOCATED ON THE BOTTOM OF 1. THE EXPOSED PAD IS LOCATED ON THE BOTTOM OF THE PACKAGE. THE EXPOSED PAD ENHANCES THE PACKAGE. THE EXPOSED PAD ENHANCES THERMAL PERFORMANCE, AND IT IS ELECTRICALLY THERMAL PERFORMANCE, AND IT IS ELECTRICALLY CONNECTED TO GND INSIDE THE PACKAGE. CONNECT
04 -0
CONNECTED TO GND INSIDE THE PACKAGE. CONNECT THE EP TO THE GROUND PLANE ON THE BOARD TO
003
THE EP TO THE GROUND PLANE ON THE BOARD TO ENSURE PROPER OPERATION.
12325
ENSURE PROPER OPERATION.
12325- Figure 3. 8-Lead LFCSP Pin Configuration Figure 4. 8-Lead SOIC Pin Configuration
Table 6. Pin Function Descriptions Pin No. Mnemonic Description
1 VREG Regulated Input Supply Voltage to LDO Amplifier. Bypass VREG to GND with a 10 μF or greater capacitor. 2 VOUT Regulated Output Voltage. Bypass VOUT to GND with a 10 μF or greater capacitor. 3 BYP Low Noise Bypass Capacitor. Connect a 1 μF capacitor from the BYP pin to GND to reduce noise. Do not connect a load to ground. 4 GND Ground Connection. 5 REF_SENSE Reference Sense. Connect Pin 5 to the REF pin. Do not connect Pin 5 to VOUT or GND. 6 REF Low Noise Reference Voltage Output. Bypass REF to GND with a 1 μF capacitor. Short REF_SENSE to REF for fixed output voltages. Do not connect a load to ground. 7 EN Enable. Drive EN high to turn on the regulator; drive EN low to turn off the regulator. For automatic startup, connect EN to VIN. 8 VIN Regulator Input Supply Voltage. Bypass VIN to GND with a 10 μF or greater capacitor. EP Exposed Pad. The exposed pad is located on the bottom of the package. The exposed pad enhances thermal performance, and it is electrically connected to GND inside the package. Connect the EP to the ground plane on the board to ensure proper operation. Rev. C | Page 6 of 24 Document Outline FEATURES APPLICATIONS TYPICAL APPLICATION CIRCUIT GENERAL DESCRIPTION REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL DATA THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION APPLICATIONS INFORMATION ADIsimPOWER DESIGN TOOL CAPACITOR SELECTION Output Capacitor Input and VREG Capacitor REF Capacitor BYP Capacitor Capacitor Properties UNDERVOLTAGE LOCKOUT (UVLO) PROGRAMMABLE PRECISION ENABLE START-UP TIME REF, BYP, AND VREG PINS CURRENT-LIMIT AND THERMAL OVERLOAD PROTECTION THERMAL CONSIDERATIONS Thermal Characterization Parameter (ΨJB) PSRR PERFORMANCE PCB LAYOUT CONSIDERATIONS OUTLINE DIMENSIONS ORDERING GUIDE