Datasheet ADP322, ADP323 (Analog Devices) - 7
| Manufacturer | Analog Devices |
| Description | Triple, 200 mA, Low Noise, High PSRR Voltage Regulator |
| Pages / Page | 24 / 7 — Data Sheet. ADP322/ADP323. EN1 1. 12 GND. VBIAS 2. 11 NIC. ADP323. … |
| Revision | E |
| File Format / Size | PDF / 854 Kb |
| Document Language | English |
Data Sheet. ADP322/ADP323. EN1 1. 12 GND. VBIAS 2. 11 NIC. ADP323. VIN1/VIN2 3. 10 VIN3. FB1 4. FB3. TOP VIEW. (Not to Scale). NOTES
Model Line for this Datasheet
Text Version of Document
Data Sheet ADP322/ADP323 N2 N3 C C E E NI NI 16 15 14 13 EN1 1 12 GND VBIAS 2 11 NIC ADP323 VIN1/VIN2 3 10 VIN3 FB1 4 9 FB3 5 6 7 8 T1 T2 B2 T3 F OU OU OU V V V TOP VIEW (Not to Scale) NOTES
054
1. NIC = NOT INTERNALLY CONNECTED. 2. CONNECT EXPOSED PAD TO GROUND PLANE.
09288- Figure 4. ADP323 Pin Configuration
Table 6. ADP323 Pin Function Descriptions Pin No. Mnemonic Description
1 EN1 Enable Input for Regulator 1. Drive EN1 high to turn on Regulator 1; drive it low to turn off Regulator 1. For automatic startup, connect EN1 to VBIAS. 2 VBIAS Input Voltage Bias Supply. Bypass VBIAS to GND with a 1 µF or greater capacitor. 3 VIN1/VIN2 Regulator Input Supply for Output Voltage 1 and Output Voltage 2. Bypass VIN1/VIN2 to GND with a 1 µF or greater capacitor. 4 FB1 Connect the midpoint of the voltage divider from VOUT1 to GND to set VOUT1. 5 VOUT1 Regulated Output Voltage 1. Connect a 1 µF or greater output capacitor between VOUT1 and GND. 6 VOUT2 Regulated Output Voltage 2. Connect a 1 µF or greater output capacitor between VOUT2 and GND. 7 FB2 Connect the midpoint of the voltage divider from VOUT2 to GND to set VOUT2. 8 VOUT3 Regulated Output Voltage 3. Connect a 1 µF or greater output capacitor between VOUT3 and GND. 9 FB3 Connect the midpoint of the voltage divider from VOUT3 to GND to set VOUT3. 10 VIN3 Regulator Input Supply for Output Voltage 3. Bypass VIN3 to GND with a 1 µF or greater capacitor. 11 NIC Not Internally Connected. This pin is not connected internally. 12 GND Ground Pin. 13 NIC Not Internally Connected. This pin is not connected internally. 14 NIC Not Internally Connected. This pin is not connected internally. 15 EN3 Enable Input for Regulator 3. Drive EN3 high to turn on Regulator 3; drive it low to turn off Regulator 3. For automatic startup, connect EN3 to VBIAS. 16 EN2 Enable Input for Regulator 2. Drive EN3 high to turn on Regulator 2; drive it low to turn off Regulator 2. For automatic startup, connect EN2 to VBIAS. EP Exposed pad for enhanced thermal performance. Connect to copper ground plane. Rev. E | Page 7 of 24 Document Outline FEATURES APPLICATIONS TYPICAL APPLICATION CIRCUITS GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS INPUT AND OUTPUT CAPACITOR, RECOMMENDED SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL DATA THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION APPLICATIONS INFORMATION ADIsimPOWER DESIGN TOOL CAPACITOR SELECTION Output Capacitor Input Bypass Capacitor Input and Output Capacitor Properties UNDERVOLTAGE LOCKOUT ENABLE FEATURE NOISE REDUCTION OF THE ADP323 IN ADJUSTABLE MODE CURRENT-LIMIT AND THERMAL OVERLOAD PROTECTION THERMAL CONSIDERATIONS PRINTED CIRCUIT BOARD LAYOUT CONSIDERATIONS OUTLINE DIMENSIONS ORDERING GUIDE NOTES
054
1. NIC = NOT INTERNALLY CONNECTED. 2. CONNECT EXPOSED PAD TO GROUND PLANE.
09288- Figure 4. ADP323 Pin Configuration
Table 6. ADP323 Pin Function Descriptions Pin No. Mnemonic Description
1 EN1 Enable Input for Regulator 1. Drive EN1 high to turn on Regulator 1; drive it low to turn off Regulator 1. For automatic startup, connect EN1 to VBIAS. 2 VBIAS Input Voltage Bias Supply. Bypass VBIAS to GND with a 1 µF or greater capacitor. 3 VIN1/VIN2 Regulator Input Supply for Output Voltage 1 and Output Voltage 2. Bypass VIN1/VIN2 to GND with a 1 µF or greater capacitor. 4 FB1 Connect the midpoint of the voltage divider from VOUT1 to GND to set VOUT1. 5 VOUT1 Regulated Output Voltage 1. Connect a 1 µF or greater output capacitor between VOUT1 and GND. 6 VOUT2 Regulated Output Voltage 2. Connect a 1 µF or greater output capacitor between VOUT2 and GND. 7 FB2 Connect the midpoint of the voltage divider from VOUT2 to GND to set VOUT2. 8 VOUT3 Regulated Output Voltage 3. Connect a 1 µF or greater output capacitor between VOUT3 and GND. 9 FB3 Connect the midpoint of the voltage divider from VOUT3 to GND to set VOUT3. 10 VIN3 Regulator Input Supply for Output Voltage 3. Bypass VIN3 to GND with a 1 µF or greater capacitor. 11 NIC Not Internally Connected. This pin is not connected internally. 12 GND Ground Pin. 13 NIC Not Internally Connected. This pin is not connected internally. 14 NIC Not Internally Connected. This pin is not connected internally. 15 EN3 Enable Input for Regulator 3. Drive EN3 high to turn on Regulator 3; drive it low to turn off Regulator 3. For automatic startup, connect EN3 to VBIAS. 16 EN2 Enable Input for Regulator 2. Drive EN3 high to turn on Regulator 2; drive it low to turn off Regulator 2. For automatic startup, connect EN2 to VBIAS. EP Exposed pad for enhanced thermal performance. Connect to copper ground plane. Rev. E | Page 7 of 24 Document Outline FEATURES APPLICATIONS TYPICAL APPLICATION CIRCUITS GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS INPUT AND OUTPUT CAPACITOR, RECOMMENDED SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL DATA THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION APPLICATIONS INFORMATION ADIsimPOWER DESIGN TOOL CAPACITOR SELECTION Output Capacitor Input Bypass Capacitor Input and Output Capacitor Properties UNDERVOLTAGE LOCKOUT ENABLE FEATURE NOISE REDUCTION OF THE ADP323 IN ADJUSTABLE MODE CURRENT-LIMIT AND THERMAL OVERLOAD PROTECTION THERMAL CONSIDERATIONS PRINTED CIRCUIT BOARD LAYOUT CONSIDERATIONS OUTLINE DIMENSIONS ORDERING GUIDE NOTES
