Datasheet ADP320 (Analog Devices) - 3
Manufacturer | Analog Devices |
Description | Triple, 200 mA, Low Noise, High PSRR Voltage Regulator |
Pages / Page | 21 / 3 — Data Sheet. ADP320. SPECIFICATIONS. Table 1. Parameter. Symbol. … |
Revision | C |
File Format / Size | PDF / 1.1 Mb |
Document Language | English |
Data Sheet. ADP320. SPECIFICATIONS. Table 1. Parameter. Symbol. Conditions. Min. Typ. Max. Unit
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Data Sheet ADP320 SPECIFICATIONS
VIN1/VIN2 = VIN3 = (VOUT + 0.5 V) or 1.8 V (whichever is greater), VBIAS = 2.5 V, EN1, EN2, EN3 = VBIAS, IOUT1 = IOUT2 = IOUT3 = 10 mA, CIN = COUT1 = COUT2 = COUT3 = 1 µF, and TA = 25°C, unless otherwise noted.
Table 1. Parameter Symbol Conditions Min Typ Max Unit
INPUT BIAS VOLTAGE RANGE VBIAS TJ = −40°C to +125°C 2.5 5.5 V INPUT LDO VOLTAGE RANGE VIN1/VIN2/ VIN3 TJ = −40°C to +125°C 1.8 5.5 V GROUND CURRENT WITH ALL IGND IOUT = 0 µA 85 µA REGULATORS ON IOUT = 0 µA, TJ = −40°C to +125°C 160 µA IOUT = 10 mA 120 µA IOUT = 10 mA, TJ = −40°C to +125°C 220 µA IOUT = 200 mA 250 µA IOUT = 200 mA, TJ = −40°C to +125°C 380 µA INPUT BIAS CURRENT IBIAS 66 µA TJ = −40°C to +125°C 140 µA SHUTDOWN CURRENT IGND-SD EN1 = EN2 = EN3 = GND 0.1 µA EN1 = EN2 = EN3 = GND, TJ = −40°C to +125°C 2.5 µA OUTPUT VOLTAGE ACCURACY VOUT −1 +1 % 100 µA < IOUT < 200 mA, VIN = (VOUT + 0.5 V) to 5.5 V, −2 +2 % TJ = −40°C to +125°C LINE REGULATION ∆VOUT/∆VIN VIN = (VOUT + 0.5 V) to 5.5 V 0.01 %/V VIN = (VOUT + 0.5 V) to 5.5 V, TJ = −40°C to +125°C −0.03 +0.03 %/V LOAD REGULATION1 ∆VOUT/∆IOUT IOUT = 1 mA to 200 mA 0.001 %/mA IOUT = 1 mA to 200 mA, TJ = −40°C to +125°C 0.005 %/mA DROPOUT VOLTAGE2 VDROPOUT VOUT = 3.3 V mV IOUT = 10 mA 6 mV IOUT = 10 mA, TJ = −40°C to +125°C 9 mV IOUT = 200 mA 110 mV IOUT = 200 mA, TJ = −40°C to +125°C 170 mV START-UP TIME3 TSTART-UP VOUT = 3.3 V, all VOUT initial y off, enable one 240 µs VOUT = 0.8 V 100 µs VOUT = 3.3 V, one VOUT initial y on, enable second 160 µs VOUT = 0.8 V 20 µs CURRENT LIMIT THRESHOLD4 ILIMIT 250 360 600 mA THERMAL SHUTDOWN Thermal Shutdown Threshold TSSD TJ rising 155 °C Thermal Shutdown Hysteresis TSSD-HYS 15 °C EN INPUT EN Input Logic High VIH 2.5 V ≤ VBIAS ≤ 5.5 V 1.2 V EN Input Logic Low VIL 2.5 V ≤ VBIAS ≤ 5.5 V 0.4 V EN Input Leakage Current VI-LEAKAGE EN1 = EN2 = EN3 = VIN or GND 0.1 µA EN1 = EN2 = EN3 = VIN or GND, TJ = −40°C to +125°C 1 µA UNDERVOLTAGE LOCKOUT UVLO Input Bias Voltage (VBIAS) Rising UVLORISE 2.45 V Input Bias Voltage (VBIAS) Falling UVLOFALL 2.0 V Hysteresis UVLOHYS 180 mV OUTPUT NOISE OUTNOISE 10 Hz to 100 kHz, VIN = 5 V, VOUT = 3.3 V 50 µV rms 10 Hz to 100 kHz, VIN = 5 V, VOUT = 2.8 V 43 µV rms 10 Hz to 100 kHz, VIN = 3.6 V, VOUT = 2.5 V 40 µV rms 10 Hz to 100 kHz, VIN = 3.6 V, VOUT = 1.2 V 24 µV rms Rev. C | Page 3 of 21 Document Outline Features Applications Typical Application Circuits General Description Revision History Specifications Input and Output Capacitor, Recommended Specifications Absolute Maximum Ratings THERMAL DATA Thermal Resistance ESD Caution Pin Configurations and Function Descriptions Typical Performance Characteristics Theory of Operation Applications Information ADIsimPower Design Tool Capacitor Selection Output Capacitor Input Bypass Capacitor Input and Output Capacitor Properties Undervoltage Lockout Enable Feature Current-Limit and Thermal Overload Protection Thermal Considerations Printed Circuit Board Layout Considerations Outline Dimensions Ordering Guide