Data SheetADP1740/ADP1741ABSOLUTE MAXIMUM RATINGS Table 3. board design is required. The value of θJA may vary, depending ParameterRating on PCB material, layout, and environmental conditions. The specified values of θ VIN to GND −0.3 V to +4.0 V JA are based on a 4-layer, 4 in × 3 in circuit board. Refer to JEDEC JESD51-7 for detailed information about VOUT to GND −0.3 V to VIN board construction. For more information, see the AN-772 EN to GND −0.3 V to VIN Application Note, A Design and Manufacturing Guide for the SS to GND −0.3 V to VIN Lead Frame Chip Scale Package (LFCSP), at www.analog.com. PG to GND −0.3 V to +4.0 V SENSE/ADJ to GND −0.3 V to VIN ΨJB is the junction-to-board thermal characterization parameter Storage Temperature Range −65°C to +150°C with units of °C/W. ΨJB of the package is based on modeling and Junction Temperature Range −40°C to +125°C calculation using a 4-layer board. The JEDEC JESD51-12 Junction Temperature 150°C document, Guidelines for Reporting and Using Electronic Package Soldering Conditions JEDEC J-STD-020 Thermal Information, states that thermal characterization Stresses at or above those listed under Absolute Maximum parameters are not the same as thermal resistances. ΨJB measures the component power flowing through multiple thermal paths Ratings may cause permanent damage to the product. This is a rather than through a single path, as in thermal resistance (θ stress rating only; functional operation of the product at these JB). Therefore, Ψ or any other conditions above those indicated in the operational JB thermal paths include convection from the top of the package, as wel as radiation from the package, factors that section of this specification is not implied. Operation beyond make Ψ the maximum operating conditions for extended periods may JB more useful in real-world applications. Maximum affect product reliability. junction temperature (TJ) is calculated from the board temper- ature (TB) and the power dissipation (PD) using the following THERMAL DATA formula: Absolute maximum ratings apply only individually, not in TJ = TB + (PD × ΨJB) combination. The ADP1740/ADP1741 may be damaged when Refer to the JEDEC JESD51-8 and JESD51-12 documents for junction temperature limits are exceeded. Monitoring ambient more detailed information about Ψ temperature does not guarantee that the junction temperature is JB. within the specified temperature limits. In applications with THERMAL RESISTANCE high power dissipation and poor PCB thermal resistance, the maximum ambient temperature may need to be derated. In θJA and ΨJB are specified for the worst-case conditions, that is, a applications with moderate power dissipation and low PCB device soldered in a circuit board for surface-mount packages. thermal resistance, the maximum ambient temperature can Table 4. Thermal Resistance exceed the maximum limit as long as the junction temperature is within specification limits. Package TypeθJAΨJBUnit 16-Lead LFCSP with Exposed Pad 42 25.5 °C/W The junction temperature (TJ) of the device is dependent on the ambient temperature (T A), the power dissipation of the device (PD), and the junction-to-ambient thermal resistance of the ESD CAUTION package (θJA). TJ is calculated using the following formula: TJ = TA + (PD × θJA) The junction-to-ambient thermal resistance (θJA) of the package is based on modeling and calculation using a 4-layer board. The junction-to-ambient thermal resistance is highly dependent on the application and board layout. In applications where high maximum power dissipation exists, close attention to thermal Rev. H | Page 5 of 20 Document Outline FEATURES APPLICATIONS TYPICAL APPLICATION CIRCUITS GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS INPUT AND OUTPUT CAPACITOR, RECOMMENDED SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL DATA THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION SOFT START FUNCTION ADJUSTABLE OUTPUT VOLTAGE (ADP1741) ENABLE FEATURE POWER-GOOD FEATURE REVERSE CURRENT PROTECTION FEATURE APPLICATIONS INFORMATION CAPACITOR SELECTION Output Capacitor Input Bypass Capacitor Input and Output Capacitor Properties UNDERVOLTAGE LOCKOUT CURRENT-LIMIT AND THERMAL OVERLOAD PROTECTION THERMAL CONSIDERATIONS PCB LAYOUT CONSIDERATIONS OUTLINE DIMENSIONS ORDERING GUIDE