Datasheet AD8421 (Analog Devices) - 21

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Data Sheet AD8421 REFERENCE TERMINAL Common-Mode Rejection Ratio over Frequency
The output voltage of the AD8421 is developed with respect to Poor layout can cause some of the common-mode signals to the potential on the reference terminal. This can be used to sense be converted to differential signals before reaching the in-amp. the ground at the load, thereby taking advantage of the CMRR to Such conversions occur when one input path has a frequency reject ground noise or to introduce a precise offset to the signal response that is different from the other. To maintain high CMRR at the output. For example, a voltage source can be tied to the REF over frequency, closely match the input source impedance and pin to level shift the output, allowing the AD8421 to drive a single- capacitance of each path. Place additional source resistance in supply ADC. The REF pin is protected with ESD diodes and the input path (for example, input protection resistors) close to should not exceed either +VS or −VS by more than 0.3 V. the in-amp inputs, to minimize the interaction of the resistance with parasitic capacitance from the PCB traces. For best performance, maintain a source impedance to the REF terminal that is below 1 Ω. As shown in Figure 61, the Parasitic capacitance at the gain setting pins (RG) can also affect reference terminal, REF, is at one end of a 10 kΩ resistor. CMRR over frequency. If the board design has a component at Additional impedance at the REF terminal adds to this 10 kΩ the gain setting pins (for example, a switch or jumper), choose resistor and results in amplification of the signal connected to a component such that the parasitic capacitance is as small as the positive input. The amplification from the additional R possible. REF can be calculated as follows:
Power Supplies and Grounding
2(10 kΩ + RREF)/(20 kΩ + RREF) Use a stable dc voltage to power the instrumentation amplifier. Only the positive signal path is amplified; the negative path is Noise on the supply pins can adversely affect performance. unaffected. This uneven amplification degrades CMRR. Place a 0.1 μF capacitor as close as possible to each supply pin.
INCORRECT CORRECT
Because the length of the bypass capacitor leads is critical at high frequency, surface-mount capacitors are recommended. Any parasitic inductance in the bypass ground trace works against
AD8421 AD8421
the low impedance that is created by the bypass capacitor. As
REF REF V
shown in Figure 64, a 10 μF capacitor can be used farther away
V
from the device. For these larger value capacitors, which are
+
intended to be effective at lower frequencies, the current return
OP1177
path distance is less critical. In most cases, the 10 μF capacitor
–
8 can be shared by other local precision integrated circuits. -05 23 101
+VS
Figure 62. Driving the Reference Pin
INPUT VOLTAGE RANGE 0.1µF 10µF
The 3-op-amp architecture of the AD8421 applies gain in the
+IN
first stage before removing the common-mode voltage in the
V R OUT G AD8421
difference amplifier stage. Internal nodes between the first and
LOAD
second stages (Node 1 and Node 2 in Figure 61) experience
–IN REF
a combination of a gained signal, a common-mode signal, and a diode drop. The voltage supplies can limit the combined signal,
0.1µF 10µF
even when the individual input and output signals are not limited. 60 -0 Figure 10 through Figure 13 show this limitation in detail.
–VS
123 10 Figure 64. Supply Decoupling, REF, and Output Referred to Local Ground
LAYOUT
A ground plane layer helps to reduce parasitic inductances, which To ensure optimum performance of the AD8421 at the PCB level, minimizes voltage drops with changes in current. The area of care must be taken in the design of the board layout. The pins of the current path is directly proportional to the magnitude of the AD8421 are arranged in a logical manner to aid in this task. parasitic inductances and, therefore, the impedance of the path at high frequency. Large changes in currents in an inductive
–IN 1 8 +VS R
decoupling path or ground return create unwanted effects due
2 7 G VOUT R
to the coupling of such changes into the amplifier inputs.
3 6 G REF +IN 4 5 –VS AD8421
Because load currents flow from the supplies, the load should be
TOP VIEW
059 connected at the same physical location as the bypass capacitor 23-
(Not to Scale)
101 grounds. Figure 63. Pin Configuration Diagram Rev. 0 | Page 21 of 28 Document Outline FEATURES APPLICATIONS PIN CONNECTION DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS AR AND BR GRADES ARM AND BRM GRADES ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION ARCHITECTURE GAIN SELECTION RG Power Dissipation REFERENCE TERMINAL INPUT VOLTAGE RANGE LAYOUT Common-Mode Rejection Ratio over Frequency Power Supplies and Grounding Reference Pin INPUT BIAS CURRENT RETURN PATH INPUT VOLTAGES BEYOND THE SUPPLY RAILS Input Voltages Beyond the Maximum Ratings RADIO FREQUENCY INTERFERENCE (RFI) CALCULATING THE NOISE OF THE INPUT STAGE Source Resistance Noise Voltage Noise of the Instrumentation Amplifier Current Noise of the Instrumentation Amplifier Total Noise Density Calculation APPLICATIONS INFORMATION DIFFERENTIAL OUTPUT CONFIGURATION DRIVING AN ADC OUTLINE DIMENSIONS ORDERING GUIDE