Datasheet AD8251 (Analog Devices) - 2
| Manufacturer | Analog Devices |
| Description | 10 MHz, G = 1, 2, 4, 8 iCMOS Programmable Gain Instrumentation Amplifier |
| Pages / Page | 24 / 2 — AD8251. TABLE OF CONTENTS. REVISION HISTORY. 11/10—Rev. A to Rev. B. … |
| Revision | B |
| File Format / Size | PDF / 646 Kb |
| Document Language | English |
AD8251. TABLE OF CONTENTS. REVISION HISTORY. 11/10—Rev. A to Rev. B. 5/08—Rev. 0 to Rev. A. 5/07—Revision 0: Initial Version
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AD8251 TABLE OF CONTENTS
Features .. 1 Power Supply Regulation and Bypassing .. 18 Applications... 1 Input Bias Current Return Path ... 18 General Description ... 1 Input Protection ... 18 Functional Block Diagram .. 1 Reference Terminal .. 19 Revision History ... 2 Common-Mode Input Voltage Range ... 19 Specifications... 3 Layout .. 19 Timing Diagram ... 5 RF Interference ... 20 Absolute Maximum Ratings.. 6 Driving an ADC ... 20 Maximum Power Dissipation ... 6 Applications... 21 ESD Caution.. 6 Differential Output .. 21 Pin Configuration and Function Descriptions... 7 Setting Gains with a Microcontroller .. 21 Typical Performance Characteristics ... 8 Data Acquisition... 22 Theory of Operation .. 16 Outline Dimensions ... 23 Gain Selection ... 16 Ordering Guide .. 23
REVISION HISTORY 11/10—Rev. A to Rev. B
Changes to Table 2...3 Changes to Voltage Offset, Offset RTI VOS, Average TC Changes to Table 3...6 Parameter in Table 2... 3 Inserted Figure 17; Renumbered Sequentially ..9 Updated Outline Dimensions ... 23 Inserted Figure 29... 11 Changes to Timing for Latched Gain Mode Section ... 17
5/08—Rev. 0 to Rev. A
Changes to Table 1.. 1
5/07—Revision 0: Initial Version
Rev. B | Page 2 of 24 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING DIAGRAM ABSOLUTE MAXIMUM RATINGS MAXIMUM POWER DISSIPATION ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION GAIN SELECTION Transparent Gain Mode Latched Gain Mode Timing for Latched Gain Mode POWER SUPPLY REGULATION AND BYPASSING INPUT BIAS CURRENT RETURN PATH INPUT PROTECTION REFERENCE TERMINAL COMMON-MODE INPUT VOLTAGE RANGE LAYOUT Grounding Coupling Noise Common-Mode Rejection RF INTERFERENCE DRIVING AN ADC APPLICATIONS DIFFERENTIAL OUTPUT SETTING GAINS WITH A MICROCONTROLLER DATA ACQUISITION OUTLINE DIMENSIONS ORDERING GUIDE
AD8251 TABLE OF CONTENTS
Features .. 1 Power Supply Regulation and Bypassing .. 18 Applications... 1 Input Bias Current Return Path ... 18 General Description ... 1 Input Protection ... 18 Functional Block Diagram .. 1 Reference Terminal .. 19 Revision History ... 2 Common-Mode Input Voltage Range ... 19 Specifications... 3 Layout .. 19 Timing Diagram ... 5 RF Interference ... 20 Absolute Maximum Ratings.. 6 Driving an ADC ... 20 Maximum Power Dissipation ... 6 Applications... 21 ESD Caution.. 6 Differential Output .. 21 Pin Configuration and Function Descriptions... 7 Setting Gains with a Microcontroller .. 21 Typical Performance Characteristics ... 8 Data Acquisition... 22 Theory of Operation .. 16 Outline Dimensions ... 23 Gain Selection ... 16 Ordering Guide .. 23
REVISION HISTORY 11/10—Rev. A to Rev. B
Changes to Table 2...3 Changes to Voltage Offset, Offset RTI VOS, Average TC Changes to Table 3...6 Parameter in Table 2... 3 Inserted Figure 17; Renumbered Sequentially ..9 Updated Outline Dimensions ... 23 Inserted Figure 29... 11 Changes to Timing for Latched Gain Mode Section ... 17
5/08—Rev. 0 to Rev. A
Changes to Table 1.. 1
5/07—Revision 0: Initial Version
Rev. B | Page 2 of 24 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING DIAGRAM ABSOLUTE MAXIMUM RATINGS MAXIMUM POWER DISSIPATION ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION GAIN SELECTION Transparent Gain Mode Latched Gain Mode Timing for Latched Gain Mode POWER SUPPLY REGULATION AND BYPASSING INPUT BIAS CURRENT RETURN PATH INPUT PROTECTION REFERENCE TERMINAL COMMON-MODE INPUT VOLTAGE RANGE LAYOUT Grounding Coupling Noise Common-Mode Rejection RF INTERFERENCE DRIVING AN ADC APPLICATIONS DIFFERENTIAL OUTPUT SETTING GAINS WITH A MICROCONTROLLER DATA ACQUISITION OUTLINE DIMENSIONS ORDERING GUIDE
