Datasheet AD8251 (Analog Devices) - 7
| Manufacturer | Analog Devices |
| Description | 10 MHz, G = 1, 2, 4, 8 iCMOS Programmable Gain Instrumentation Amplifier |
| Pages / Page | 24 / 7 — AD8251. PIN CONFIGURATION AND FUNCTION DESCRIPTIONS. –IN 1. 10 +IN. DGND … |
| Revision | B |
| File Format / Size | PDF / 646 Kb |
| Document Language | English |
AD8251. PIN CONFIGURATION AND FUNCTION DESCRIPTIONS. –IN 1. 10 +IN. DGND 2. REF. –VS 3. TOP VIEW. (Not to Scale). A0 4. OUT. A1 5
Model Line for this Datasheet
Text Version of Document
AD8251 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS –IN 1 10 +IN DGND 2 9 REF AD8251 –VS 3 8 +V TOP VIEW S (Not to Scale) A0 4 7 OUT
5 -00
A1 5 6 WR
287 06 Figure 5. Pin Configuration
Table 4. Pin Function Descriptions Pin No. Mnemonic Description
1 −IN Inverting Input Terminal. True differential input. 2 DGND Digital Ground. 3 −VS Negative Supply Terminal. 4 A0 Gain Setting Pin (LSB). 5 A1 Gain Setting Pin (MSB). 6 WR Write Enable. 7 OUT Output Terminal. 8 +VS Positive Supply Terminal. 9 REF Reference Voltage Terminal. 10 +IN Noninverting Input Terminal. True differential input. Rev. B | Page 7 of 24 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING DIAGRAM ABSOLUTE MAXIMUM RATINGS MAXIMUM POWER DISSIPATION ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION GAIN SELECTION Transparent Gain Mode Latched Gain Mode Timing for Latched Gain Mode POWER SUPPLY REGULATION AND BYPASSING INPUT BIAS CURRENT RETURN PATH INPUT PROTECTION REFERENCE TERMINAL COMMON-MODE INPUT VOLTAGE RANGE LAYOUT Grounding Coupling Noise Common-Mode Rejection RF INTERFERENCE DRIVING AN ADC APPLICATIONS DIFFERENTIAL OUTPUT SETTING GAINS WITH A MICROCONTROLLER DATA ACQUISITION OUTLINE DIMENSIONS ORDERING GUIDE
5 -00
A1 5 6 WR
287 06 Figure 5. Pin Configuration
Table 4. Pin Function Descriptions Pin No. Mnemonic Description
1 −IN Inverting Input Terminal. True differential input. 2 DGND Digital Ground. 3 −VS Negative Supply Terminal. 4 A0 Gain Setting Pin (LSB). 5 A1 Gain Setting Pin (MSB). 6 WR Write Enable. 7 OUT Output Terminal. 8 +VS Positive Supply Terminal. 9 REF Reference Voltage Terminal. 10 +IN Noninverting Input Terminal. True differential input. Rev. B | Page 7 of 24 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING DIAGRAM ABSOLUTE MAXIMUM RATINGS MAXIMUM POWER DISSIPATION ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION GAIN SELECTION Transparent Gain Mode Latched Gain Mode Timing for Latched Gain Mode POWER SUPPLY REGULATION AND BYPASSING INPUT BIAS CURRENT RETURN PATH INPUT PROTECTION REFERENCE TERMINAL COMMON-MODE INPUT VOLTAGE RANGE LAYOUT Grounding Coupling Noise Common-Mode Rejection RF INTERFERENCE DRIVING AN ADC APPLICATIONS DIFFERENTIAL OUTPUT SETTING GAINS WITH A MICROCONTROLLER DATA ACQUISITION OUTLINE DIMENSIONS ORDERING GUIDE
