Datasheet AD8250 (Analog Devices) - 10

AD8250 Data Sheet 15 A) 10 n ( T 8 N 10 6 URRE C T I 4 E 5 B– S ) F /V F 2 V µ D O 0 0 RR ( AN IB+ CM NT –2 ∆ –5 –4 IOS CURRE S –6 A –10 BI
9
–8
04
UT
8- 28
–15
06
INP –10 –40 –25 –10 5 20 35 50 65 80 95 110 125
19
–50 –30 –10 10 30 50 70 90 110 130
0 8-
TEMPERATURE (°C)
28
TEMPERATURE (°C)
06 Figure 18. Input Bias Current and Offset Current vs. Temperature Figure 21. CMRR vs. Temperature, G = 1
140 25 G = 10 G = 5 G = 10 20 120 15 G = 5 100 ) B) G = 2 G = 1 d B 10 d 80 ( G = 2 RR ( IN 5 CM GA 60 G = 1 0 40 –5 20 –10 1 10 100 1k 10k 100k 1M
20 23 0
1k 10k 100k 1M 10M 100M
0 8- 8-
FREQUENCY (Hz)
28
FREQUENCY (Hz)
28 06 06 Figure 19. CMRR vs. Frequency Figure 22. Gain vs. Frequency
140 40 f = 1kHz G = 10 G = 5 30 120 ) IV /D 20 pm 100 10p ( 10 B) G = 2 Y d G = 1 IT 80 R 0 RR ( A E CM IN L –10 60 ON N IN –20 40 GA –30
24 0 8- 28
20 –40
06
1 10 100 1k 10k 100k 1M
21 0
–10 –8 –6 –4 –2 0 2 4 6 8 10
8-
FREQUENCY (Hz)
28
OUTPUT VOLTAGE (V)
06 Figure 20. CMRR vs. Frequency, 1 kΩ Source Imbalance Figure 23. Gain Nonlinearity vs. Output Voltage, G = 1, RL = 10 kΩ, 2 kΩ, 600 Ω Rev. C | Page 10 of 24 Document Outline Features Applications General Description Functional Block Diagram Revision History Specifications Timing Diagram Absolute Maximum Ratings Maximum Power Dissipation ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Theory of Operation Gain Selection Transparent Gain Mode Latched Gain Mode Timing for Latched Gain Mode Power Supply Regulation and Bypassing Input Bias Current Return Path Input Protection Reference Terminal Common-Mode Input Voltage Range Layout Grounding Coupling Noise Common-Mode Rejection RF Interference Driving an ADC Applications Differential Output Setting Gains with a Microcontroller Data Acquisition Outline Dimensions Ordering Guide