Datasheet AD8553 (Analog Devices) - 10
| Manufacturer | Analog Devices |
| Description | 1.8 V to 5 V Auto-Zero, In-Amp with Shutdown |
| Pages / Page | 20 / 10 — AD8553. VCC = 1.8V. GAIN = 1. 120. 160. 200. 240. 280. 320. 360. 0.4 0.8 … |
| Revision | A |
| File Format / Size | PDF / 336 Kb |
| Document Language | English |
AD8553. VCC = 1.8V. GAIN = 1. 120. 160. 200. 240. 280. 320. 360. 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0 4.4 4.8. VCC = 5.0V. VCC = 1.8V,
Model Line for this Datasheet
Text Version of Document
AD8553 VCC = 1.8V VCC = 1.8V GAIN = 1 GAIN = 1 N N IO IO T T LA LA PU PU PO PO
3 23 0 -03 4- 4 47 47 05 05
0 40 80 120 160 200 240 280 320 360 0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0 4.4 4.8
Figure 26. Input Offset Voltage (μV) Figure 28. Input Offset Voltage Drift (μV/°C)
VCC = 5.0V VCC = 1.8V, GAIN = 100 G = 10, 100, 1000 10kHz FILTER IV IV /D /D V V n 1kHz FILTER 200 500m
6 29 -03 0 4- 74 47 054 05
500µs/DIV 10SEC/DIV
Figure 27. 0.01 Hz to 10 Hz Voltage Noise Figure 29. Large Signal Step Response Rev. A | Page 10 of 20 Document Outline FEATURES APPLICATIONS PIN CONFIGURATION GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ELECTRICAL CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION HIGH PSR AND CMR 1/f NOISE CORRECTION APPLICATIONS GAIN SELECTION (GAIN-SETTING RESISTORS) REFERENCE CONNECTION DISABLE FUNCTION OUTPUT FILTERING CLOCK FEEDTHROUGH LOW IMPEDANCE OUTPUT MAXIMIZING PERFORMANCE THROUGH PROPER LAYOUT POWER SUPPLY BYPASSING INPUT OVERVOLTAGE PROTECTION CAPACITIVE LOAD DRIVE CIRCUIT DIAGRAMS/CONNECTIONS OUTLINE DIMENSIONS ORDERING GUIDE
3 23 0 -03 4- 4 47 47 05 05
0 40 80 120 160 200 240 280 320 360 0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0 4.4 4.8
Figure 26. Input Offset Voltage (μV) Figure 28. Input Offset Voltage Drift (μV/°C)
VCC = 5.0V VCC = 1.8V, GAIN = 100 G = 10, 100, 1000 10kHz FILTER IV IV /D /D V V n 1kHz FILTER 200 500m
6 29 -03 0 4- 74 47 054 05
500µs/DIV 10SEC/DIV
Figure 27. 0.01 Hz to 10 Hz Voltage Noise Figure 29. Large Signal Step Response Rev. A | Page 10 of 20 Document Outline FEATURES APPLICATIONS PIN CONFIGURATION GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ELECTRICAL CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION HIGH PSR AND CMR 1/f NOISE CORRECTION APPLICATIONS GAIN SELECTION (GAIN-SETTING RESISTORS) REFERENCE CONNECTION DISABLE FUNCTION OUTPUT FILTERING CLOCK FEEDTHROUGH LOW IMPEDANCE OUTPUT MAXIMIZING PERFORMANCE THROUGH PROPER LAYOUT POWER SUPPLY BYPASSING INPUT OVERVOLTAGE PROTECTION CAPACITIVE LOAD DRIVE CIRCUIT DIAGRAMS/CONNECTIONS OUTLINE DIMENSIONS ORDERING GUIDE
