Datasheet AD622 (Analog Devices) - 7
| Manufacturer | Analog Devices |
| Description | Low Cost Instrumentation Amplifier |
| Pages / Page | 16 / 7 — Data Sheet. AD622. 180. VS = ±15V G = 10. 160. p) p-. 140. ) B. G (. 120. … |
| Revision | E |
| File Format / Size | PDF / 282 Kb |
| Document Language | English |
Data Sheet. AD622. 180. VS = ±15V G = 10. 160. p) p-. 140. ) B. G (. 120. G = 1000. WIN S. 100. IVE PSR T. G = 100. OLTA. T V U. G = 10. G = 1. 0.1. 10k. 100k
Model Line for this Datasheet
Text Version of Document
Data Sheet AD622 180 30 VS = ±15V G = 10 160 p) p- 140 V ) B G ( 20 (d 120 G = 1000 WIN S 100 GE IVE PSR T G = 100 SI 80 OLTA PO 10 T V U 60 G = 10 TP OU 40 G = 1 20 0 0.1 1 10 100 1k 10k 100k 1M
008
10 100 1k 10k
011
FREQUENCY (Hz) LOAD RESISTANCE (Ω)
00777- 00777- Figure 8. Positive PSR vs. Frequency, RTI (G = 1 to 1000) Figure 11. Output Voltage Swing vs. Load Resistance
180 20 160 140 15 ) ) B s µ (d 120 ( TO 0.1% E 100 10 G TIM IVE PSR T G = 1000 A 80 TTLIN EG E N S G = 100 60 5 40 G = 10 G = 1 20 0 0.1 1 10 100 1k 10k 100k 1M
009
0 5 10 15 20
012
FREQUENCY (Hz) OUTPUT STEP SIZE (V)
00777- 00777- Figure 9. Negative PSR vs. Frequency, RTI (G = 1 to 1000) Figure 12. Settling Time vs. Step Size (G = 1)
1000 1000 100 ) s µ 100 ( E V) (V/ 10 IN G TIM A G TTLIN E 10 S 1 0.1 1 100 1k 10k 100k 1M 10M
010
1 10 100 1000
013
FREQUENCY (Hz) GAIN
00777- 00777- Figure 10. Gain vs. Frequency Figure 13. Settling Time to 0.1% vs. Gain, for a 10 V Step Rev. E | Page 7 of 16 Document Outline Features Applications Pin Configuration General Description Revision History Specifications Absolute Maximum Ratings Thermal Resistance ESD Caution Typical Performance Characteristics Theory of Operation Make vs. Buy: A Typical Application Error Budget Gain Selection Input and Output Offset Voltage Reference Terminal Input Protection RF Interference Ground Returns for Input Bias Currents Outline Dimensions Ordering Guide
008
10 100 1k 10k
011
FREQUENCY (Hz) LOAD RESISTANCE (Ω)
00777- 00777- Figure 8. Positive PSR vs. Frequency, RTI (G = 1 to 1000) Figure 11. Output Voltage Swing vs. Load Resistance
180 20 160 140 15 ) ) B s µ (d 120 ( TO 0.1% E 100 10 G TIM IVE PSR T G = 1000 A 80 TTLIN EG E N S G = 100 60 5 40 G = 10 G = 1 20 0 0.1 1 10 100 1k 10k 100k 1M
009
0 5 10 15 20
012
FREQUENCY (Hz) OUTPUT STEP SIZE (V)
00777- 00777- Figure 9. Negative PSR vs. Frequency, RTI (G = 1 to 1000) Figure 12. Settling Time vs. Step Size (G = 1)
1000 1000 100 ) s µ 100 ( E V) (V/ 10 IN G TIM A G TTLIN E 10 S 1 0.1 1 100 1k 10k 100k 1M 10M
010
1 10 100 1000
013
FREQUENCY (Hz) GAIN
00777- 00777- Figure 10. Gain vs. Frequency Figure 13. Settling Time to 0.1% vs. Gain, for a 10 V Step Rev. E | Page 7 of 16 Document Outline Features Applications Pin Configuration General Description Revision History Specifications Absolute Maximum Ratings Thermal Resistance ESD Caution Typical Performance Characteristics Theory of Operation Make vs. Buy: A Typical Application Error Budget Gain Selection Input and Output Offset Voltage Reference Terminal Input Protection RF Interference Ground Returns for Input Bias Currents Outline Dimensions Ordering Guide
