Datasheet AOZ5311NQI (Alpha & Omega) - 6
| Manufacturer | Alpha & Omega |
| Description | High-Current, High-Performance DrMOS Power Module |
| Pages / Page | 17 / 6 — AOZ5311NQI. Electrical Characteristics(4). Symbol. Parameter. Conditions. … |
| File Format / Size | PDF / 1.3 Mb |
| Document Language | English |
AOZ5311NQI. Electrical Characteristics(4). Symbol. Parameter. Conditions. Min. Typ. Max. Units. GENERAL. INPUT SUPPLY AND UVLO. PWM INPUT
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AOZ5311NQI Electrical Characteristics(4)
TA = 25°C to 125°C. Typical values reflect 25°C ambient temperature; VIN = 12V, VCC= PVCC= DISB# = 5V, unless otherwise specified.
Symbol Parameter Conditions Min. Typ. Max. Units GENERAL
VIN Power Stage Power Supply 2.5 20 V VCC Low Voltage Bias Supply PVCC = VCC 4.5 5.5 V R (5) JC Reference to High-Side MOSFET 2.5 °C/W Thermal Resistance temperature rise R (5) JA Freq = 300kHz. AOS Demo Board 12.5 °C/W
INPUT SUPPLY AND UVLO
VCC_UVLO VCC Rising 3.5 3.9 V Under-Voltage Lockout VCC_HYST VCC Hysteresis 400 mV DISB# = 0V 1 A SMOD# = 5V, PWM = 0V 550 A IVCC Control Circuit Bias Current SMOD# = 0V, PWM = 0V 535 A SMOD# = 0V, PWM =1.65V 430 A PWM = 400kHz, 20% Duty Cycle 13 mA IPVCC Drive Circuit Operating Current PWM = 1MHz, 20% Duty Cycle 33 mA
PWM INPUT
VPWMH Logic High Input Voltage 2.7 V VPWML Logic Low Input Voltage 0.72 V IPWM_SRC PWM = 0V -150 A PWM Pin Input Current IPWM_SNK PWM = 3.3V 150 A VTRI PWM Input Tri-State Window 1.35 1.95 V VPMW_ PWM Tri-State Voltage Clamp PWM = Floating 1.65 V FLOAT
DISB# INPUT
VDISB#_ Enable Input Voltage 2.0 V ON VDISB#_ Disable Input Voltage 0.8 V OFF RDISB# DISB# Input Resistance Pull-Down Resistor 850 k
SMOD# INPUT
VSMOD#_H Logic High Input Voltage 2.0 V VSMOD#_L Logic Low Input Voltage 0.8 V RSMOD# SMOD# Input Resistance Pull-Down Resistor 850 k
GATE DRIVER TIMING
tPDLU PWM to High-Side Gate PWM: H→L, VSWH: H→L 30 ns tPDLL PWM to Low-Side Gate PWM: L H, GL: H L 25 ns tPDHU Low-side to High-Side Gate Deadtime GL: H L, GH(6): L H 15 ns tPDHL High-Side to Low-side Gate Deadtime VSWH: H 1V, GL: L H 13 ns tTSSHD Tri-State Shutdown Delay PWM: L VTRI, GL: H L and PWM: H VTRI, VSWH: H L 25 ns tTSEXIT Tri-State Propagation Delay PWM: VTRI H, VSWH: L H PWM: VTRI L, GL: L H 35 ns tLGMIN Low-Side Minimum On-Time SMOD# = L 350 ns Rev. 1.0 May 2019
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TA = 25°C to 125°C. Typical values reflect 25°C ambient temperature; VIN = 12V, VCC= PVCC= DISB# = 5V, unless otherwise specified.
Symbol Parameter Conditions Min. Typ. Max. Units GENERAL
VIN Power Stage Power Supply 2.5 20 V VCC Low Voltage Bias Supply PVCC = VCC 4.5 5.5 V R (5) JC Reference to High-Side MOSFET 2.5 °C/W Thermal Resistance temperature rise R (5) JA Freq = 300kHz. AOS Demo Board 12.5 °C/W
INPUT SUPPLY AND UVLO
VCC_UVLO VCC Rising 3.5 3.9 V Under-Voltage Lockout VCC_HYST VCC Hysteresis 400 mV DISB# = 0V 1 A SMOD# = 5V, PWM = 0V 550 A IVCC Control Circuit Bias Current SMOD# = 0V, PWM = 0V 535 A SMOD# = 0V, PWM =1.65V 430 A PWM = 400kHz, 20% Duty Cycle 13 mA IPVCC Drive Circuit Operating Current PWM = 1MHz, 20% Duty Cycle 33 mA
PWM INPUT
VPWMH Logic High Input Voltage 2.7 V VPWML Logic Low Input Voltage 0.72 V IPWM_SRC PWM = 0V -150 A PWM Pin Input Current IPWM_SNK PWM = 3.3V 150 A VTRI PWM Input Tri-State Window 1.35 1.95 V VPMW_ PWM Tri-State Voltage Clamp PWM = Floating 1.65 V FLOAT
DISB# INPUT
VDISB#_ Enable Input Voltage 2.0 V ON VDISB#_ Disable Input Voltage 0.8 V OFF RDISB# DISB# Input Resistance Pull-Down Resistor 850 k
SMOD# INPUT
VSMOD#_H Logic High Input Voltage 2.0 V VSMOD#_L Logic Low Input Voltage 0.8 V RSMOD# SMOD# Input Resistance Pull-Down Resistor 850 k
GATE DRIVER TIMING
tPDLU PWM to High-Side Gate PWM: H→L, VSWH: H→L 30 ns tPDLL PWM to Low-Side Gate PWM: L H, GL: H L 25 ns tPDHU Low-side to High-Side Gate Deadtime GL: H L, GH(6): L H 15 ns tPDHL High-Side to Low-side Gate Deadtime VSWH: H 1V, GL: L H 13 ns tTSSHD Tri-State Shutdown Delay PWM: L VTRI, GL: H L and PWM: H VTRI, VSWH: H L 25 ns tTSEXIT Tri-State Propagation Delay PWM: VTRI H, VSWH: L H PWM: VTRI L, GL: L H 35 ns tLGMIN Low-Side Minimum On-Time SMOD# = L 350 ns Rev. 1.0 May 2019
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