Datasheet ADSP-21566, ADSP-21567, ADSP-21569 (Analog Devices) - 3
| Manufacturer | Analog Devices |
| Description | SHARC+ Single Core High Performance DSP (Up to 1 GHz) |
| Pages / Page | 98 / 3 — ADSP-21566/21567/21569. GENERAL DESCRIPTION. Table 1. Processor Features. … |
| File Format / Size | PDF / 2.7 Mb |
| Document Language | English |
ADSP-21566/21567/21569. GENERAL DESCRIPTION. Table 1. Processor Features. Processor Feature. ADSP-21566. ADSP-21567. ADSP-21569
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ADSP-21566/21567/21569 GENERAL DESCRIPTION
Reaching speeds of up to 1 GHz, the ADSP-2156x processors SHARC+ core include cache enhancements and branch predic- are members of the SHARC® family of products. The ADSP- tion, while maintaining instruction set compatibility to previous 2156x processor is based on the SHARC+® single core. The SHARC products. ADSP-2156x SHARC processors are members of the SIMD By integrating a rich set of industry-leading system peripherals SHARC family of digital signal processors (DSPs) that feature and memory (see Table 1), the SHARC+ processor is the plat- Analog Devices, Inc., Super Harvard Architecture. These 32- form of choice for applications that require programmability bit/40-bit/64-bit floating-point processors are optimized for similar to reduced instruction set computing (RISC), multime- high performance audio/floating-point applications with large dia support, and leading edge signal processing in one on-chip static random-access memory (SRAM), multiple inter- integrated package. These applications span a wide array of nal buses that eliminate input/output (I/O) bottlenecks, and markets, including automotive, professional audio, and indus- innovative digital audio interfaces (DAI). New additions to the trial-based applications that require high floating-point performance.
Table 1. Processor Features Processor Feature ADSP-21566 ADSP-21567 ADSP-21569
SHARC+ Core (MHz Maximum)1 400 600, 800 800, 1000 SHARC L1 SRAM (kB) 640 640 640 System Memory L2 SRAM (kB) 256 512 1024 DDR3 and DDR3L2 Controller (16-Bit) 1 1 1 DAI (Includes SRU) 2 2 2 Full SPORTs 2 × 4 2 × 4 2 × 4 S/PDIF Rx/Tx 2 × 1 2 × 1 2 × 1 ASRCs 2 × 4 2 × 4 2 × 4 Precision Clock Generators 2 × 2 2 × 2 2 × 2 Buffers 2 × 14 2 × 14 2 × 14 Hardware Accelerators FIR/IIR Yes Yes Yes Security Crypto Engine Yes Yes Yes I2C (TWI) 6 6 6 SPI 1 1 1 Quad SPI 2 2 2 Octal SPI 1 1 1 UARTs 3 3 3 Link Port 2 2 2 General-Purpose Timer3 10 10 10 General-Purpose Counter 1 1 1 Watchdog Timer 2 2 2 MLB 3-pin Automotive models only GPIO Ports Port A to Port C GPIO + DAI Pins 40 + 28 Package Options 400-ball CSP_BGA 1 The values refer to different speed grades. 2 DDR3L is supported in 1.35 V mode of operation. 3 Refer to Table 14 for internal timer signal routing. Rev. 0 | Page 3 of 98 | March 2020 Document Outline System Features Memory Additional Features Applications Table of Contents Revision History General Description SHARC Processor L1 Memory L1 Master and Slave Ports L1 On-Chip Memory Bandwidth Instruction and Data Cache Core Memory-Mapped Registers (CMMR) SHARC+ Core Architecture Single-Instruction, Multiple Data (SIMD) Computational Engine Independent Parallel Computation Units Core Timer Data Register File Context Switch Universal Registers Data Address Generators (DAG) With Zero Overhead Hardware Circular Buffer Support Flexible Instruction Set Architecture (ISA) Variable Instruction Set Architecture (VISA) Single-Cycle Fetch of Instructional Four Operands Core Event Controller (CEC) Instruction Conflict Cache Branch Target Buffer (BTB)/Branch Predictor (BP) Addressing Spaces Additional Features System Infrastructure System L2 Memory One Time Programmable Memory (OTP) I/O Memory Space System Memory Map System Crossbars (SCBs) Direct Memory Access (DMA) Memory Direct Memory Access (MDMA) Extended Memory DMA Cyclic Redundant Code (CRC) Protection Event Handling System Event Controller (SEC) Trigger Routing Unit (TRU) Security Features Cryptographic Hardware Accelerators System Protection Unit (SPU) System Memory Protection Unit (SMPU) Security Features Disclaimer Safety Features Multiparity Bit Protected SHARC+ Core L1 Memories Error Correcting Code (ECC) Protected L2 Memories Parity Protected Peripheral Memories Cyclic Redundant Code (CRC) Protected Memories Signal Watchdogs System Event Controller (SEC) Memory Error Controller (MEC) Processor Peripherals Dynamic Memory Controller (DMC) Digital Audio Interface (DAI) Serial Port (SPORT) Asynchronous Sample Rate Converter (ASRC) S/PDIF-Compatible Digital Audio Receiver/Transmitter Precision Clock Generators (PCG) Universal Asynchronous Receiver/Transmitter (UART) Ports Serial Peripheral Interface (SPI) Ports Octal Serial Peripheral Interface (OSPI) Port Link Port (LP) Timers General-Purpose (GP) Timers (TIMER) Watchdog Timer (WDT) General-Purpose Counters (CNT) Media Local Bus (MediaLB) 2-Wire Controller Interface (TWI) General-Purpose I/O (GPIO) Pin Interrupts System Acceleration Finite Impulse Response (FIR) Accelerator Infinite Impulse Response (IIR) Accelerator System Design Clock Management Reset Control Unit (RCU) Clock Generation Unit (CGU) System Crystal Oscillator Clock Distribution Unit (CDU) Clock Out/External Clock Booting Power Supplies Power Management Power-Up and Power-Down Sequencing Target Board JTAG Emulator Connector System Debug System Watchpoint Unit (SWU) Debug Access Port (DAP) Development Tools Integrated Development Environments (IDEs) EZ-KIT Evaluation Board EZ-KIT Evaluation Kits Software Add Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains ADSP-2156x Detailed Signal Descriptions 400-Ball CSP_BGA Signal Descriptions GPIO Multiplexing for 400-Ball CSP_BGA Package 120-Lead LQFP Signal Descriptions GPIO Multiplexing for 120-Lead LQFP ADSP-2156x Designer Quick Reference Specifications Operating Conditions Clock Related Operating Conditions Electrical Characteristics Total Internal Power Dissipation Application Dependent Current Clock Current Data Transmission Current Absolute Maximum Ratings ESD Caution Timing Specifications Power-Up Reset Timing Clock and Reset Timing Link Ports (LPs) Serial Ports (SPORTs) Asynchronous Sample Rate Converter (ASRC)—Serial Input Port Asynchronous Sample Rate Converter (ASRC)—Serial Output Port SPI Port—Master Timing SPI0, SPI1, and SPI2 SPI Port—Slave Timing SPI0, SPI1, and SPI2 SPI Port—SPIx_RDY Slave Timing SPI Port—Open Drain Mode (ODM) Timing SPI Port—SPIx_RDY Master Timing OSPI Port—Master Timing OSPI0 Precision Clock Generator (PCG) (Direct Pin Routing) General-Purpose IO Port Timing General-Purpose I/O Timer Cycle Timing DAIx Pin to DAIx Pin Direct Routing (DAI0 Block and DAI1 Block) Up/Down Counter/Rotary Encoder Timing Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing Sony/Philips Digital Interface (S/PDIF) Transmitter S/PDIF Transmitter Serial Input Waveforms S/PDIF Transmitter Input Data Timing Oversampling Clock (TxCLK) Switching Characteristics S/PDIF Receiver Internal Digital PLL Mode MediaLB (MLB) Program Trace Macrocell (PTM) Timing Debug Interface (JTAG Emulation Port) Timing Output Drive Currents Test Conditions Output Enable Time Measurement Output Disable Time Measurement Capacitive Loading Environmental Conditions ADSP-2156x 400-Ball BGA Ball Assignments ADSP-2156x 400-Ball BGA Ball Assignments (Numerical by Ball Number) ADSP-2156x 400-Ball BGA Ball Assignments (Alphabetical by Pin Name) Configuration of the 400-Ball CSP_BGA ADSP-2156x 120-Lead LQFP Lead Assignments ADSP-2156x 120-Lead LQFP Lead Assignments (Numerical by Lead Number) ADSP-2156x 120-Lead LQFP Lead Assignments (Alphabetical by Pin Name) Configuration of the 120-Lead LQFP Lead Configuration Outline Dimensions Surface-Mount Design Planned Automotive Production Products Planned Production Products Ordering Guide
ADSP-21566/21567/21569 GENERAL DESCRIPTION
Reaching speeds of up to 1 GHz, the ADSP-2156x processors SHARC+ core include cache enhancements and branch predic- are members of the SHARC® family of products. The ADSP- tion, while maintaining instruction set compatibility to previous 2156x processor is based on the SHARC+® single core. The SHARC products. ADSP-2156x SHARC processors are members of the SIMD By integrating a rich set of industry-leading system peripherals SHARC family of digital signal processors (DSPs) that feature and memory (see Table 1), the SHARC+ processor is the plat- Analog Devices, Inc., Super Harvard Architecture. These 32- form of choice for applications that require programmability bit/40-bit/64-bit floating-point processors are optimized for similar to reduced instruction set computing (RISC), multime- high performance audio/floating-point applications with large dia support, and leading edge signal processing in one on-chip static random-access memory (SRAM), multiple inter- integrated package. These applications span a wide array of nal buses that eliminate input/output (I/O) bottlenecks, and markets, including automotive, professional audio, and indus- innovative digital audio interfaces (DAI). New additions to the trial-based applications that require high floating-point performance.
Table 1. Processor Features Processor Feature ADSP-21566 ADSP-21567 ADSP-21569
SHARC+ Core (MHz Maximum)1 400 600, 800 800, 1000 SHARC L1 SRAM (kB) 640 640 640 System Memory L2 SRAM (kB) 256 512 1024 DDR3 and DDR3L2 Controller (16-Bit) 1 1 1 DAI (Includes SRU) 2 2 2 Full SPORTs 2 × 4 2 × 4 2 × 4 S/PDIF Rx/Tx 2 × 1 2 × 1 2 × 1 ASRCs 2 × 4 2 × 4 2 × 4 Precision Clock Generators 2 × 2 2 × 2 2 × 2 Buffers 2 × 14 2 × 14 2 × 14 Hardware Accelerators FIR/IIR Yes Yes Yes Security Crypto Engine Yes Yes Yes I2C (TWI) 6 6 6 SPI 1 1 1 Quad SPI 2 2 2 Octal SPI 1 1 1 UARTs 3 3 3 Link Port 2 2 2 General-Purpose Timer3 10 10 10 General-Purpose Counter 1 1 1 Watchdog Timer 2 2 2 MLB 3-pin Automotive models only GPIO Ports Port A to Port C GPIO + DAI Pins 40 + 28 Package Options 400-ball CSP_BGA 1 The values refer to different speed grades. 2 DDR3L is supported in 1.35 V mode of operation. 3 Refer to Table 14 for internal timer signal routing. Rev. 0 | Page 3 of 98 | March 2020 Document Outline System Features Memory Additional Features Applications Table of Contents Revision History General Description SHARC Processor L1 Memory L1 Master and Slave Ports L1 On-Chip Memory Bandwidth Instruction and Data Cache Core Memory-Mapped Registers (CMMR) SHARC+ Core Architecture Single-Instruction, Multiple Data (SIMD) Computational Engine Independent Parallel Computation Units Core Timer Data Register File Context Switch Universal Registers Data Address Generators (DAG) With Zero Overhead Hardware Circular Buffer Support Flexible Instruction Set Architecture (ISA) Variable Instruction Set Architecture (VISA) Single-Cycle Fetch of Instructional Four Operands Core Event Controller (CEC) Instruction Conflict Cache Branch Target Buffer (BTB)/Branch Predictor (BP) Addressing Spaces Additional Features System Infrastructure System L2 Memory One Time Programmable Memory (OTP) I/O Memory Space System Memory Map System Crossbars (SCBs) Direct Memory Access (DMA) Memory Direct Memory Access (MDMA) Extended Memory DMA Cyclic Redundant Code (CRC) Protection Event Handling System Event Controller (SEC) Trigger Routing Unit (TRU) Security Features Cryptographic Hardware Accelerators System Protection Unit (SPU) System Memory Protection Unit (SMPU) Security Features Disclaimer Safety Features Multiparity Bit Protected SHARC+ Core L1 Memories Error Correcting Code (ECC) Protected L2 Memories Parity Protected Peripheral Memories Cyclic Redundant Code (CRC) Protected Memories Signal Watchdogs System Event Controller (SEC) Memory Error Controller (MEC) Processor Peripherals Dynamic Memory Controller (DMC) Digital Audio Interface (DAI) Serial Port (SPORT) Asynchronous Sample Rate Converter (ASRC) S/PDIF-Compatible Digital Audio Receiver/Transmitter Precision Clock Generators (PCG) Universal Asynchronous Receiver/Transmitter (UART) Ports Serial Peripheral Interface (SPI) Ports Octal Serial Peripheral Interface (OSPI) Port Link Port (LP) Timers General-Purpose (GP) Timers (TIMER) Watchdog Timer (WDT) General-Purpose Counters (CNT) Media Local Bus (MediaLB) 2-Wire Controller Interface (TWI) General-Purpose I/O (GPIO) Pin Interrupts System Acceleration Finite Impulse Response (FIR) Accelerator Infinite Impulse Response (IIR) Accelerator System Design Clock Management Reset Control Unit (RCU) Clock Generation Unit (CGU) System Crystal Oscillator Clock Distribution Unit (CDU) Clock Out/External Clock Booting Power Supplies Power Management Power-Up and Power-Down Sequencing Target Board JTAG Emulator Connector System Debug System Watchpoint Unit (SWU) Debug Access Port (DAP) Development Tools Integrated Development Environments (IDEs) EZ-KIT Evaluation Board EZ-KIT Evaluation Kits Software Add Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains ADSP-2156x Detailed Signal Descriptions 400-Ball CSP_BGA Signal Descriptions GPIO Multiplexing for 400-Ball CSP_BGA Package 120-Lead LQFP Signal Descriptions GPIO Multiplexing for 120-Lead LQFP ADSP-2156x Designer Quick Reference Specifications Operating Conditions Clock Related Operating Conditions Electrical Characteristics Total Internal Power Dissipation Application Dependent Current Clock Current Data Transmission Current Absolute Maximum Ratings ESD Caution Timing Specifications Power-Up Reset Timing Clock and Reset Timing Link Ports (LPs) Serial Ports (SPORTs) Asynchronous Sample Rate Converter (ASRC)—Serial Input Port Asynchronous Sample Rate Converter (ASRC)—Serial Output Port SPI Port—Master Timing SPI0, SPI1, and SPI2 SPI Port—Slave Timing SPI0, SPI1, and SPI2 SPI Port—SPIx_RDY Slave Timing SPI Port—Open Drain Mode (ODM) Timing SPI Port—SPIx_RDY Master Timing OSPI Port—Master Timing OSPI0 Precision Clock Generator (PCG) (Direct Pin Routing) General-Purpose IO Port Timing General-Purpose I/O Timer Cycle Timing DAIx Pin to DAIx Pin Direct Routing (DAI0 Block and DAI1 Block) Up/Down Counter/Rotary Encoder Timing Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing Sony/Philips Digital Interface (S/PDIF) Transmitter S/PDIF Transmitter Serial Input Waveforms S/PDIF Transmitter Input Data Timing Oversampling Clock (TxCLK) Switching Characteristics S/PDIF Receiver Internal Digital PLL Mode MediaLB (MLB) Program Trace Macrocell (PTM) Timing Debug Interface (JTAG Emulation Port) Timing Output Drive Currents Test Conditions Output Enable Time Measurement Output Disable Time Measurement Capacitive Loading Environmental Conditions ADSP-2156x 400-Ball BGA Ball Assignments ADSP-2156x 400-Ball BGA Ball Assignments (Numerical by Ball Number) ADSP-2156x 400-Ball BGA Ball Assignments (Alphabetical by Pin Name) Configuration of the 400-Ball CSP_BGA ADSP-2156x 120-Lead LQFP Lead Assignments ADSP-2156x 120-Lead LQFP Lead Assignments (Numerical by Lead Number) ADSP-2156x 120-Lead LQFP Lead Assignments (Alphabetical by Pin Name) Configuration of the 120-Lead LQFP Lead Configuration Outline Dimensions Surface-Mount Design Planned Automotive Production Products Planned Production Products Ordering Guide
