Datasheet ADSP-21483, ADSP-21486, ADSP-21487, ADSP-21488, ADSP-21489 (Analog Devices) - 62

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ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489 176-LEAD LQFP_EP LEAD ASSIGNMENT Table 61. ADSP-21486 176-Lead LQFP_EP Lead Assignment (Numerical by Lead Number) Lead Name Lead No. Lead Name Lead No. Lead Name Lead No. Lead Name Lead No.
DNC 1* VDD_EXT 45 DAI_P10 89 VDD_INT 133 MS0 2 DPI_P08 46 VDD_INT 90 FLAG0 134 DNC 3* DPI_P07 47 VDD_EXT 91 FLAG1 135 VDD_INT 4 VDD_INT 48 DAI_P20 92 FLAG2 136 CLK_CFG1 5 DPI_P09 49 VDD_INT 93 GND 137 ADDR0 6 DPI_P10 50 DAI_P08 94 FLAG3 138 BOOT_CFG0 7 DPI_P11 51 DAI_P14 95 GND 139 VDD_EXT 8 DPI_P12 52 DAI_P04 96 GND 140 ADDR1 9 DPI_P13 53 DAI_P18 97 VDD_EXT 141 ADDR2 10 DPI_P14 54 DAI_P17 98 GND 142 ADDR3 11 DAI_P03 55 DAI_P16 99 VDD_INT 143 ADDR4 12 DNC 56* DAI_P12 100 TRST 144 ADDR5 13 VDD_EXT 57 DAI_P15 101 GND 145 BOOT_CFG1 14 DNC 58* VDD_INT 102 EMU 146 GND 15 DNC 59* DAI_P11 103 DATA0 147 ADDR6 16 DNC 60* VDD_EXT 104 DATA1 148 ADDR7 17 DNC 61* VDD_INT 105 DATA2 149 DNC 18* VDD_INT 62 BOOT_CFG2 106 DATA3 150 DNC 19* DNC 63* VDD_INT 107 TDO 151 ADDR8 20 DNC 64* AMI_ACK 108 DATA4 152 ADDR9 21 VDD_INT 65 GND 109 VDD_EXT 153 CLK_CFG0 22 DNC 66* THD_M 110 DATA5 154 VDD_INT 23 DNC 67* THD_P 111 DATA6 155 CLKIN 24 VDD_INT 68 VDD_THD 112 VDD_INT 156 XTAL 25 DNC 69* VDD_INT 113 DATA7 157 ADDR10 26 WDTRSTO 70 VDD_INT 114 TDI 158 DNC 27* DNC 71* MS1 115 DNC 159* VDD_EXT 28 VDD_EXT 72 VDD_INT 116 VDD_EXT 160 VDD_INT 29 DAI_P07 73 WDT_CLKO 117 DATA8 161 ADDR11 30 DAI_P13 74 WDT_CLKIN 118 DATA9 162 ADDR12 31 DAI_P19 75 VDD_EXT 119 DATA10 163 ADDR17 32 DAI_P01 76 ADDR23 120 TCK 164 ADDR13 33 DAI_P02 77 ADDR22 121 DATA11 165 VDD_INT 34 VDD_INT 78 ADDR21 122 DATA12 166 ADDR18 35 DNC 79* VDD_INT 123 DATA14 167 RESETOUT/RUNRSTIN 36 DNC 80* ADDR20 124 DATA13 168 VDD_INT 37 DNC 81* ADDR19 125 VDD_INT 169 DPI_P01 38 DNC 82* VDD_EXT 126 DATA15 170 DPI_P02 39 DNC 83* ADDR16 127 DNC 171* DPI_P03 40 VDD_EXT 84 ADDR15 128 DNC 172* VDD_INT 41 VDD_INT 85 VDD_INT 129 RESET 173 DPI_P05 42 DAI_P06 86 ADDR14 130 TMS 174 DPI_P04 43 DAI_P05 87 AMI_WR 131 DNC 175* DPI_P06 44 DAI_P09 88 AMI_RD 132 VDD_INT 176 GND 177** * Do not make any electrical connection to this pin. ** Lead no. 177 (exposed pad) is the GND supply (see Figure 51 and Figure 52) for the processor; this pad must be
robustly
connected to GND. Rev. H | Page 62 of 71 | February 2020 Document Outline Features Table of Contents Revision History General Description Family Core Architecture SIMD Computational Engine Independent, Parallel Computation Units Timer Data Register File Context Switch Universal Registers Single-Cycle Fetch of Instruction and Four Operands Instruction Cache Data Address Generators With Zero-Overhead Hardware Circular Buffer Support Flexible Instruction Set Variable Instruction Set Architecture (VISA) On-Chip Memory ROM Based Security On-Chip Memory Bandwidth Family Peripheral Architecture External Memory External Port Asynchronous Memory Controller SDRAM Controller SIMD Access to External Memory VISA and ISA Access to External Memory Pulse-Width Modulation MediaLB Digital Applications Interface (DAI) Serial Ports (SPORTs) S/PDIF-Compatible Digital Audio Receiver/Transmitter Asynchronous Sample Rate Converter (SRC) Input Data Port Precision Clock Generators Digital Peripheral Interface (DPI) Serial Peripheral (Compatible) Interface (SPI) UART Port Timers 2-Wire Interface Port (TWI) I/O Processor Features DMA Controller Delay Line DMA Scatter/Gather DMA FFT Accelerator FIR Accelerator IIR Accelerator Watchdog Timer System Design Program Booting Power Supplies Static Voltage Scaling (SVS) Target Board JTAG Emulator Connector Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains Pin Function Descriptions Specifications Operating Conditions Electrical Characteristics Total Power Dissipation Absolute Maximum Ratings ESD Sensitivity Maximum Power Dissipation Timing Specifications Core Clock Requirements Voltage Controlled Oscillator (VCO) Power-Up Sequencing Clock Input Clock Signals Reset Running Reset Interrupts Core Timer Timer PWM_OUT Cycle Timing Timer WDTH_CAP Timing Watchdog Timer Timing Pin to Pin Direct Routing (DAI and DPI) Precision Clock Generator (Direct Pin Routing) Flags SDRAM Interface Timing (166 MHz SDCLK) AMI Read AMI Write Serial Ports Input Data Port (IDP) Parallel Data Acquisition Port (PDAP) Sample Rate Converter—Serial Input Port Sample Rate Converter—Serial Output Port Pulse-Width Modulation Generators (PWM) S/PDIF Transmitter S/PDIF Transmitter-Serial Input Waveforms S/PDIF Transmitter Input Data Timing Oversampling Clock (TxCLK) Switching Characteristics S/PDIF Receiver Internal Digital PLL Mode SPI Interface—Master SPI Interface—Slave Media Local Bus Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing 2-Wire Interface (TWI)—Receive and Transmit Timing JTAG Test Access Port and Emulation Output Drive Currents Test Conditions Capacitive Loading Thermal Characteristics Thermal Diode 88-Lead LFCSP_VQ Lead Assignment 100-Lead LQFP_EP Lead Assignment 176-Lead LQFP_EP Lead Assignment Outline Dimensions Surface-Mount Design Automotive Products Ordering Guide