Datasheet ADSP-21369 (Analog Devices)

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SHARC Processor ADSP-21369 SUMMARY DEDICATED AUDIO COMPONENTS High performance 32-bit/40-bit floating-point processor S/PDIF-compatible digital audio receiver/transmitter optimized for high performance audio processing 4 independent asynchronous sample rate converters (SRC) Single-instruction, multiple-data (SIMD) computational 16 PWM outputs configured as four groups of four outputs architecture ROM-based security features include On-chip memory—2M bits of on-chip SRAM and 6M bits of JTAG access to memory permitted with a 64-bit key on-chip mask programmable ROM Protected memory regions that can be assigned to limit Code compatible with all other members of the SHARC family access under program control to sensitive code 400 MHz core instruction rate with unique audiocentric PLL has a wide variety of software and hardware multi- peripherals such as the digital applications interface, plier/divider ratios S/PDIF transceiver, serial ports, 8-channel asynchronous Available in 256-ball BGA_ED and 208-lead LQFP_EP sample rate converter, precision clock generators, and packages more. For complete ordering information, see Ordering Guide . Internal Memory SIMD Core Block 0 Block 1 Block 2 Block 3 RAM/ROM RAM/ROM RAM RAM Instruction 5 stage Cache Sequencer B0D B1D B2D B3D 64-BIT 64-BIT 64-BIT 64-BIT
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DAG1/2 Timer DMD 64-BIT DMD 64-BIT PEx PEy Core Bus Internal Memory I/F Cross Bar PMD PMD 64-BIT 64-BIT IOD0 32-BIT FLAGx/IRQx/ EPD BUS 32-BIT JTAG TMREXP PERIPHERAL BUS 32-BIT IOD1 32-BIT IOD0 BUS MTM PERIPHERAL BUS EP CORE PCG TIMER UART S/PDIF PCG ASRC IDP/ SPORT CORE PWM TWI SPI/B PDAP AMI SDRAM FLAGS C-D 2-0 1-0 Tx/Rx A-D 3-0 7-0 FLAGS 3-0 7-0 DPI Routing/Pins DAI Routing/Pins External Port Pin MUX External DPI Peripherals DAI Peripherals Peripherals Port
Figure 1. Functional Block Diagram SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc.
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Document Outline Summary Dedicated Audio Components Table of Contents Revision History General Description SHARC Family Core Architecture SIMD Computational Engine Independent, Parallel Computation Units Data Register File Context Switch Universal Registers Timer Single-Cycle Fetch of Instruction and Four Operands Instruction Cache Data Address Generators with Zero-Overhead Hardware Circular Buffer Support Flexible Instruction Set On-Chip Memory On-Chip Memory Bandwidth ROM-Based Security Family Peripheral Architecture External Port SDRAM Controller External Memory Shared External Memory External Port Throughput Asynchronous Memory Controller Pulse-Width Modulation Digital Applications Interface (DAI) Serial Ports S/PDIF-Compatible Digital Audio Receiver/Transmitter Synchronous/Asynchronous Sample Rate Converter Input Data Port Precision Clock Generators Digital Peripheral Interface (DPI) Serial Peripheral (Compatible) Interface UART Port Peripheral Timers 2-Wire Interface Port (TWI) I/O Processor Features DMA Controller Delay Line DMA System Design Program Booting Power Supplies Target Board JTAG Emulator Connector Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains Pin Function Descriptions Specifications Operating Conditions Electrical Characteristics ESD Caution Maximum Power Dissipation Absolute Maximum Ratings Timing Specifications Core Clock Requirements Voltage Controlled Oscillator Power-Up Sequencing Clock Input Clock Signals Reset Interrupts Core Timer Timer PWM_OUT Cycle Timing Timer WDTH_CAP Timing Pin to Pin Direct Routing (DAI and DPI) Precision Clock Generator (Direct Pin Routing) Flags SDRAM Interface Timing (166 MHz SDCLK) SDRAM Interface Enable/Disable Timing (166 MHz SDCLK) Memory Read Memory Write Asynchronous Memory Interface (AMI) Enable/Disable Shared Memory Bus Request Serial Ports Input Data Port Parallel Data Acquisition Port (PDAP) Pulse-Width Modulation Generators Sample Rate Converter—Serial Input Port Sample Rate Converter—Serial Output Port S/PDIF Transmitter S/PDIF Transmitter—Serial Input Waveforms S/PDIF Transmitter Input Data Timing Oversampling Clock (TxCLK) Switching Characteristics S/PDIF Receiver Internal Digital PLL Mode SPI Interface—Master SPI Interface—Slave JTAG Test Access Port and Emulation Output Drive Currents Test Conditions Capacitive Loading Thermal Characteristics 256-Ball BGA_ED Pinout 208-Lead LQFP_EP Pinout Package Dimensions Surface-Mount Design Ordering Guide