Datasheet ADSP-21065L-EP (Analog Devices) - 6

ADSP-21065L-EP Enhanced Product Table 2. Pin Descriptions (Continued) Pin Type Function
FLAG11–0 I/O/A
Flag Pins.
Each is configured via control bits as either an input or output. As an input, they can be tested as a condition. As an output, they can be used to signal external peripherals. HBR I/A
Host Bus Request.
This pin must be asserted by a host processor to request control of the ADSP-21065L-EP’s external bus. When HBR is asserted in a multiprocessing system, the ADSP-21065L-EP that is bus master will relinquish the bus and assert HBG. To relinquish the bus, the ADSP-21065L-EP places the address, data, select, and strobe lines in a high impedance state. It does, however, continue to drive the SDRAM control pins. HBR has priority over all ADSP-21065L-EP bus requests (BR2–1) in a multiprocessing system. HBG I/O
Host Bus Grant.
Acknowledges an HBR bus request, indicating that the host processor may take control of the external bus. HBG is asserted by the ADSP-21065L-EP until HBR is released. In a multiprocessing system, HBG is output by the ADSP-21065L-EP bus master. CS I/A
Chip Select.
Asserted by host processor to select the ADSP-21065L-EP. REDY (O/D) O
Host Bus Acknowledge.
The ADSP-21065L-EP deasserts REDY to add wait states to an asynchronous access of its internal memory or IOP registers by a host. This pin is an open-drain output (O/D) by default; it can be programmed in the ADREDY bit of the SYSCON register to be active drive (A/D). REDY will only be output if the CS and HBR inputs are asserted. DMAR1 I/A
DMA Request 1
(DMA Channel 9). DMAR2 I/A
DMA Request 2
(DMA Channel 8). DMAG1 O/T
DMA Grant 1
(DMA Channel 9). DMAG2 O/T
DMA Grant 2
(DMA Channel 8). BR2–1 I/O/S
Multiprocessing Bus Requests.
Used by multiprocessing ADSP-21065L-EP processors to arbitrate for bus master-ship. An ADSP-21065L-EP only drives its own BRx line (corresponding to the value of its ID2–0 inputs) and monitors all others. In a uniprocessor system, tie both BRx pins to VDD. ID1–0 I
Multiprocessing ID.
Determines which multiprocessor bus request (BR1–BR2) is used by the ADSP-21065L-EP. ID = 01 corresponds to BR1, ID = 10 corresponds to BR2. ID = 00 in single-processor systems. These lines are a system configuration selection that should be hardwired or changed at reset only. CPA (O/D) I/O
Core Priority Access.
Asserting its CPA pin allows the core processor of an ADSP-21065L-EP bus slave to interrupt background DMA transfers and gain access to the external bus. CPA is an open-drain output that is connected to all ADSP-21065L-EP processors in the system. The CPA pin has an internal 5 k pull-up resistor. If core access priority is not required in a system, the CPA pin should be left unconnected. DTxX O
Data Transmit (Serial Ports 0, 1; Channels A, B).
Each DTxX pin has a 50 k internal pull-up resistor. DRxX I
Data Receive (Serial Ports 0, 1; Channels A, B).
Each DRxX pin has a 50 k internal pull-up resistor. TCLKx I/O
Transmit Clock (Serial Ports 0, 1).
Each TCLK pin has a 50 k internal pull-up resistor. RCLKx I/O
Receive Clock (Serial Ports 0, 1).
Each RCLK pin has a 50 k internal pull-up resistor. TFSx I/O
Transmit Frame Sync (Serial Ports 0, 1).
RFSx I/O
Receive Frame Sync (Serial Ports 0, 1).
BSEL I
EPROM Boot Select.
When BSEL is high, the ADSP-21065L-EP is configured for booting from an 8-bit EPROM. When BSEL is low, the BSEL and BMS inputs determine booting mode. See BMS pin description below for details. This signal is a system configuration selection that should be hardwired. BMS I/O/T*
Boot Memory Select.
Output: Used as chip select for boot EPROM devices (when BSEL = 1). In a multipro- cessor system, BMS is output by the bus master. Input: When low, indicates that no booting will occur and that ADSP-21065L-EP will begin executing instructions from external memory. See table below. This input is a system configuration selection that should be hardwired. *Three-statable only in EPROM boot mode (when BMS is an output).
BSEL BMS Booting Mode
1 Output EPROM (connect BMS to EPROM chip select.) 0 1 (Input) Host processor (HBW [SYSCON] bit selects host bus width). 0 0 (Input) No booting. Processor executes from external memory. A = Asynchronous, G = Ground, I = Input, O = Output, P = Power Supply, S = Synchronous, (A/D) = Active Drive, (O/D) = Open Drain, T = Three-State (when SBTS is asserted, or when the ADSP-21065L-EP is a bus slave) Rev. B | Page 6 of 14 | September 2017 Document Outline Summary Enhanced Product (EP) Features Features Table of Contents Revision History General Description Pin Function Descriptions Specifications Operating Conditions Absolute Maximum Ratings ESD Caution Package Marking Information Environmental Conditions Thermal Characteristics 208-LEAD MQFP Pin Configuration Outline Dimensions Ordering Guide