Datasheet K6R1016V1D (Samsung) - 3
| Manufacturer | Samsung |
| Description | CMOS SRAM |
| Pages / Page | 11 / 3 — for AT&T. K6R1016V1D. CMOS SRAM. 64K x 16 Bit High-Speed CMOS Static … |
| File Format / Size | PDF / 269 Kb |
| Document Language | English |
for AT&T. K6R1016V1D. CMOS SRAM. 64K x 16 Bit High-Speed CMOS Static RAM(3.3V Operating) FEATURES. GENERAL DESCRIPTION
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for AT&T K6R1016V1D CMOS SRAM 64K x 16 Bit High-Speed CMOS Static RAM(3.3V Operating) FEATURES GENERAL DESCRIPTION
• Fast Access Time 8,10ns(Max.) The K6R1016V1D is a 1,048,576-bit high-speed Static Random • Low Power Dissipation Access Memory organized as 65,536 words by 16 bits. Standby (TTL) : 20mA(Max.) The K6R1016V1D uses 16 common input and output lines and (CMOS) : 5mA(Max.) has at output enable pin which operates faster than address Operating K6R1016V1D- 08: 80mA(Max.) access time at read cycle. Also it allows that lower and upper K6R1016V1D-10: 65mA(Max.) byte access by data byte control (UB, LB). The device is • Single 3.3V Power Supply fabricated using SAMSUNG′s advanced CMOS process and • TTL Compatible Inputs and Outputs designed for high-speed circuit technology. It is particularly well • Fully Static Operation suited for use in high-density high-speed system applications. - No Clock or Refresh required The K6R1016V1D is packaged in a 400mil 44-pin plastic SOJ • Three State Outputs or TSOP2 forward or 48-TBGA. • Center Power/Ground Pin Configuration • Data Byte Control: LB: I/O1~ I/O8, UB: I/O9~ I/O16 • Standard Pin Configuration: K6R1016V1D-J: 44-SOJ-400 K6R1016V1D-T: 44-TSOP2-400BF K6R1016V1D-E: 48-TBGA ( 6.0mm X 7.0mm ) with 0.75mm ball pitch • Operating in Commercial and Industrial Temperature range.
FUNCTIONAL BLOCK DIAGRAM
Clk Gen. Pre-Charge Circuit A0 A1 A2 t c A3 le e Memory Array A4 S 512 Rows A5 w 128x16 Columns o A6 R A7
PIN FUNCTION
A8
Pin Name Pin Function
Data I/O Circuit & I/O1~I/O8 Cont. Column Select A0 - A15 Address Inputs Data WE Write Enable I/O9~I/O16 Cont. CS Chip Select Gen. CLK OE Output Enable A9 A10 A11 A12 A13 A14 A15 LB Lower-byte Control(I/O1~I/O8) UB Upper-byte Control(I/O9~I/O16) I/O1 ~ I/O16 Data Inputs/Outputs WE VCC Power(+3.3V) OE VSS Ground UB N.C No Connection LB CS
Revision 3.0
- 3 -
June 2002
• Fast Access Time 8,10ns(Max.) The K6R1016V1D is a 1,048,576-bit high-speed Static Random • Low Power Dissipation Access Memory organized as 65,536 words by 16 bits. Standby (TTL) : 20mA(Max.) The K6R1016V1D uses 16 common input and output lines and (CMOS) : 5mA(Max.) has at output enable pin which operates faster than address Operating K6R1016V1D- 08: 80mA(Max.) access time at read cycle. Also it allows that lower and upper K6R1016V1D-10: 65mA(Max.) byte access by data byte control (UB, LB). The device is • Single 3.3V Power Supply fabricated using SAMSUNG′s advanced CMOS process and • TTL Compatible Inputs and Outputs designed for high-speed circuit technology. It is particularly well • Fully Static Operation suited for use in high-density high-speed system applications. - No Clock or Refresh required The K6R1016V1D is packaged in a 400mil 44-pin plastic SOJ • Three State Outputs or TSOP2 forward or 48-TBGA. • Center Power/Ground Pin Configuration • Data Byte Control: LB: I/O1~ I/O8, UB: I/O9~ I/O16 • Standard Pin Configuration: K6R1016V1D-J: 44-SOJ-400 K6R1016V1D-T: 44-TSOP2-400BF K6R1016V1D-E: 48-TBGA ( 6.0mm X 7.0mm ) with 0.75mm ball pitch • Operating in Commercial and Industrial Temperature range.
FUNCTIONAL BLOCK DIAGRAM
Clk Gen. Pre-Charge Circuit A0 A1 A2 t c A3 le e Memory Array A4 S 512 Rows A5 w 128x16 Columns o A6 R A7
PIN FUNCTION
A8
Pin Name Pin Function
Data I/O Circuit & I/O1~I/O8 Cont. Column Select A0 - A15 Address Inputs Data WE Write Enable I/O9~I/O16 Cont. CS Chip Select Gen. CLK OE Output Enable A9 A10 A11 A12 A13 A14 A15 LB Lower-byte Control(I/O1~I/O8) UB Upper-byte Control(I/O9~I/O16) I/O1 ~ I/O16 Data Inputs/Outputs WE VCC Power(+3.3V) OE VSS Ground UB N.C No Connection LB CS
Revision 3.0
- 3 -
June 2002
