Datasheet K6R1016V1D (Samsung) - 6

for AT&T K6R1016V1D CMOS SRAM READ CYCLE* K6R1016V1D-08 K6R1016V1D-10 Parameter Symbol Unit Min Max Min Max
Read Cycle Time tRC 8 - 10 - ns Address Access Time tAA - 8 - 10 ns Chip Select to Output tCO - 8 - 10 ns Output Enable to Valid Output tOE - 4 - 5 ns UB, LB Access Time tBA - 4 - 5 ns Chip Enable to Low-Z Output tLZ 3 - 3 - ns Output Enable to Low-Z Output tOLZ 0 - 0 - ns UB, LB Enable to Low-Z Output tBLZ 0 - 0 - ns Chip Disable to High-Z Output tHZ 0 4 0 5 ns Output Disable to High-Z Output tOHZ 0 4 0 5 ns UB, LB Disable to High-Z Output tBHZ 0 4 0 5 ns Output Hold from Address Change tOH 3 - 3 - ns Chip Selection to Power Up Time tPU 0 - 0 - ns Chip Selection to Power DownTime tPD - 8 - 10 ns * The above parameters are also guaranteed at industrial temperature range.
WRITE CYCLE* K6R1016V1D-08 K6R1016V1D-10 Parameter Symbol Unit Min Max Min Max
Write Cycle Time tWC 8 - 10 - ns Chip Select to End of Write tCW 6 - 7 - ns Address Set-up Time tAS 0 - 0 - ns Address Valid to End of Write tAW 6 - 7 - ns Write Pulse Width(OE High) tWP 6 - 7 - ns Write Pulse Width(OE Low) tWP1 8 - 10 - ns UB, LB Valid to End of Write tBW 6 - 7 - ns Write Recovery Time tWR 0 - 0 - ns Write to Output High-Z tWHZ 0 4 0 5 ns Data to Write Time Overlap tDW 4 - 5 - ns Data Hold from Write Time tDH 0 - 0 - ns End of Write to Output Low-Z tOW 3 - 3 - ns * The above parameters are also guaranteed at industrial temperature range.
TIMING DIAGRAMS TIMING WAVEFORM OF READ CYCLE(1)
(Address Controlled, CS=OE=VIL, WE=VIH, UB, LB=VIL) tRC
Address
tAA tOH
Data Out
Previous Valid Data Valid Data
Revision 3.0
- 6 -
June 2002