Datasheet ADA4075-2 (Analog Devices) - 6

ADA4075-2 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, unless otherwise noted.
250 250 VSY = ±15V VSY = ±5V VCM = 0V VCM = 0V BASED ON 600 OP AMPS BASED ON 600 OP AMPS 200 SOIC PACKAGE 200 SOIC PACKAGE RS RS IE IE IF IF L 150 L 150 P P AM AM F F R O 100 R O 100 BE BE NUM NUM 50 50 0 0 –1.0 –0.5 0 0.5 1.0 –1.0 –0.5 0 0.5 1.0
003 006
VOS (mV) V
07642-
OS (mV)
07642- Figure 3. Input Offset Voltage Distribution Figure 6. Input Offset Voltage Distribution
100 100 VSY = ±15V VSY = ±5V VCM = 0V VCM = 0V BASED ON 300 OP AMPS BASED ON 300 OP AMPS 80 LFCSP PACKAGE 80 LFCSP PACKAGE RS RS IE IE IF IF L 60 L 60 P P AM AM F F R O 40 R O 40 BE BE NUM NUM 20 20 0 0 –1.0 –0.5 0 0.5 1.0
040
–1.0 –0.5 0 0.5 1.0
042
VOS (mV) V
07642-
OS (mV)
07642- Figure 4. Input Offset Voltage Distribution Figure 7. Input Offset Voltage Distribution
70 80 VSY = ±15V VSY = ±5V –40°C ≤ TA ≤ +125°C –40°C ≤ TA ≤ +125°C 60 BASED ON 200 OP AMPS 70 BASED ON 200 OP AMPS SOIC PACKAGE SOIC PACKAGE 60 RS 50 RS IE IE IF IF L 50 L P 40 P AM AM 40 F F 30 R O R O 30 BE BE 20 NUM NUM 20 10 10 0 0 –2.0 –1.6 –1.2 –0.8 –0.4 0 0.4 0.8 1.2 1.6 2.0 –2.0 –1.6 –1.2 –0.8 –0.4 0 0.4 0.8 1.2 1.6 2.0
004 007
TCVOS (μV/°C) TCV
07642-
OS (μV/°C)
07642- Figure 5. Input Offset Voltage Drift Distribution Figure 8. Input Offset Voltage Drift Distribution Rev. C | Page 6 of 24 Document Outline Features Applications Pin Configurations General Description Table of Contents Revision History Specifications Absolute Maximum Ratings Thermal Resistance Power Sequencing ESD Caution Typical Performance Characteristics Applications Information Input Protection Total Harmonic Distortion Phase Reversal DAC Output Filter Balanced Line Driver Balanced Line Receiver Low Noise Parametric Equalizer Schematic Outline Dimensions Ordering Guide