Datasheet LT8550 (Analog Devices) - 10
| Manufacturer | Analog Devices |
| Description | 4-Phase DC/DC Expander with Internal Gate Drivers for Buck Converters |
| Pages / Page | 34 / 10 — PIN FUNCTIONS (QFN) REG (Pin 3):. TGSL (Pin 19):. BG1, BG2, BG3, BG4 … |
| File Format / Size | PDF / 3.2 Mb |
| Document Language | English |
PIN FUNCTIONS (QFN) REG (Pin 3):. TGSL (Pin 19):. BG1, BG2, BG3, BG4 (Pins 11, 10, 2, 1):. BGBUF (Pin 12):
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PIN FUNCTIONS (QFN) REG (Pin 3):
Output of REG LDO. Power supply for gate top MOSFET’s state. For a slave LT8550, connect this pin drivers. Decouple this pin to ground with a minimum to the master LT8550’s TGBUF pin. 4.7µF low ESR ceramic capacitor. Connect this pin to the
TGSL (Pin 19):
Lower Rail of Primary Channel Top Gate external PMOS drain side. Sense Circuit. For a master LT8550, connect this pin to
BG1, BG2, BG3, BG4 (Pins 11, 10, 2, 1):
Bottom Gate the primary channel top MOSFET’s source. This pin, com- Driver Output. These pins drive the gates of the bottom bined with TGSR, TGSH pins, is to sense the primary N-channel MOSFETs. Voltage swing at these pins is from channel top MOSFET’s state. For a slave LT8550, connect ground to REG. this pin to ground.
BGBUF (Pin 12):
Logic Output Pin. This pin is pulled up
CLK1, CLK2 (Pins 21, 20):
Clock Pin. These two pins to REG when BGSH is at logic high, and it is pulled down are used to synchronize the primary channel to all other to ground when BGSH is at logic low. For a slave LT8550, channels. See the Applications Information section for leave this pin floating. See the Applications Information more information. section for more information.
BGSH (Pin 22):
Logic Input of Primary Channel Bottom
TGBUF (Pin 13):
Logic Output Pin. For a master LT8550, Gate Sense Circuit. For a master LT8550, connect this this pin is pulled up to REG voltage when (TGSH-TGSL) pin to the primary channel bottom MOSFET’s gate. This is at logic high, and it is pulled down to ground when pin is to sense the primary channel bottom MOSFET’s (TGSH-TGSL) is at logic low. For a slave LT8550, leave state. For a slave LT8550, connect this pin to the master this pin floating. See the Applications Information section LT8550’s BGBUF pin. for more information.
SYNC (Pin 23):
To synchronize the switching frequency to
BST1, BST2, BST3, BST4 (Pins 14, 7, 6, 52):
Boosted an outside clock, simply drive this pin with a clock. The Floating Driver Supply. The (+) terminal of the boost-strap high voltage level of the clock must exceed 1.2V, and the capacitor is connected to this pin. This pin swings from a low level must be less than 0.8V. Drive this pin to less diode voltage drop below REG up to VIN + REG. than 0.8V to revert to the internal free-running clock. See
TG1, TG2, TG3, TG4 (Pins 15, 8, 5, 51):
Top Gate Driver the Typical Applications section. Output. This is the output of a floating driver with a volt-
PHS1, PHS2 (Pins 25, 24):
Phase Selection Pin. These age swing equal to REG superimposed on the switch node pins, combined with PHS3 and RT/MS, set the switch- voltage. ing frequency and the phase of each channel. PHS1 and
SW1, SW2, SW3, SW4 (Pins 16, 9, 4, 50):
Switch Node. PHS2 are three-level input pins, they can be floated, set Voltage swing at these pins is from a diode voltage drop to REG or ground. When the PHS1/PHS2 is floating, add below ground to V a 1nF cap from PHS1/PHS2 to ground. See the Operation IN. section for more information.
TGSR (Pin 17):
The Rail of Primary Channel Top Gate Sense Circuit. For a master LT8550, connect this pin to
RT/MS (Pin 26):
Timing Resistor Pin and Master Slave the primary channel top gate driver’s boost node. This pin, Selection Pin. This pin, combined with PHS1, PHS2 and combined with TGSH, TGSL pins, is to sense the primary PHS3, sets the switching frequency and the phase of channel top MOSFET’s state. For a slave LT8550, connect each channel. Connecting a resistor to ground sets the this pin to REG. chip as master LT8550. Connecting this pin to the REG pin sets the chip as slave LT8550. See the Applications
TGSH (Pin 18):
Input of Primary Channel Top Gate Sense Information section for more information. Circuit. For a master LT8550, connect this pin to the pri- mary channel top MOSFET’s gate. This pin, combined with TGSR, TGSL pins, is to sense the primary channel Rev. 0 10 For more information www.analog.com
PIN FUNCTIONS (QFN) REG (Pin 3):
Output of REG LDO. Power supply for gate top MOSFET’s state. For a slave LT8550, connect this pin drivers. Decouple this pin to ground with a minimum to the master LT8550’s TGBUF pin. 4.7µF low ESR ceramic capacitor. Connect this pin to the
TGSL (Pin 19):
Lower Rail of Primary Channel Top Gate external PMOS drain side. Sense Circuit. For a master LT8550, connect this pin to
BG1, BG2, BG3, BG4 (Pins 11, 10, 2, 1):
Bottom Gate the primary channel top MOSFET’s source. This pin, com- Driver Output. These pins drive the gates of the bottom bined with TGSR, TGSH pins, is to sense the primary N-channel MOSFETs. Voltage swing at these pins is from channel top MOSFET’s state. For a slave LT8550, connect ground to REG. this pin to ground.
BGBUF (Pin 12):
Logic Output Pin. This pin is pulled up
CLK1, CLK2 (Pins 21, 20):
Clock Pin. These two pins to REG when BGSH is at logic high, and it is pulled down are used to synchronize the primary channel to all other to ground when BGSH is at logic low. For a slave LT8550, channels. See the Applications Information section for leave this pin floating. See the Applications Information more information. section for more information.
BGSH (Pin 22):
Logic Input of Primary Channel Bottom
TGBUF (Pin 13):
Logic Output Pin. For a master LT8550, Gate Sense Circuit. For a master LT8550, connect this this pin is pulled up to REG voltage when (TGSH-TGSL) pin to the primary channel bottom MOSFET’s gate. This is at logic high, and it is pulled down to ground when pin is to sense the primary channel bottom MOSFET’s (TGSH-TGSL) is at logic low. For a slave LT8550, leave state. For a slave LT8550, connect this pin to the master this pin floating. See the Applications Information section LT8550’s BGBUF pin. for more information.
SYNC (Pin 23):
To synchronize the switching frequency to
BST1, BST2, BST3, BST4 (Pins 14, 7, 6, 52):
Boosted an outside clock, simply drive this pin with a clock. The Floating Driver Supply. The (+) terminal of the boost-strap high voltage level of the clock must exceed 1.2V, and the capacitor is connected to this pin. This pin swings from a low level must be less than 0.8V. Drive this pin to less diode voltage drop below REG up to VIN + REG. than 0.8V to revert to the internal free-running clock. See
TG1, TG2, TG3, TG4 (Pins 15, 8, 5, 51):
Top Gate Driver the Typical Applications section. Output. This is the output of a floating driver with a volt-
PHS1, PHS2 (Pins 25, 24):
Phase Selection Pin. These age swing equal to REG superimposed on the switch node pins, combined with PHS3 and RT/MS, set the switch- voltage. ing frequency and the phase of each channel. PHS1 and
SW1, SW2, SW3, SW4 (Pins 16, 9, 4, 50):
Switch Node. PHS2 are three-level input pins, they can be floated, set Voltage swing at these pins is from a diode voltage drop to REG or ground. When the PHS1/PHS2 is floating, add below ground to V a 1nF cap from PHS1/PHS2 to ground. See the Operation IN. section for more information.
TGSR (Pin 17):
The Rail of Primary Channel Top Gate Sense Circuit. For a master LT8550, connect this pin to
RT/MS (Pin 26):
Timing Resistor Pin and Master Slave the primary channel top gate driver’s boost node. This pin, Selection Pin. This pin, combined with PHS1, PHS2 and combined with TGSH, TGSL pins, is to sense the primary PHS3, sets the switching frequency and the phase of channel top MOSFET’s state. For a slave LT8550, connect each channel. Connecting a resistor to ground sets the this pin to REG. chip as master LT8550. Connecting this pin to the REG pin sets the chip as slave LT8550. See the Applications
TGSH (Pin 18):
Input of Primary Channel Top Gate Sense Information section for more information. Circuit. For a master LT8550, connect this pin to the pri- mary channel top MOSFET’s gate. This pin, combined with TGSR, TGSL pins, is to sense the primary channel Rev. 0 10 For more information www.analog.com
