Datasheet LTC3871, LTC3871-1 (Analog Devices) - 9
| Manufacturer | Analog Devices |
| Description | Bidirectional PolyPhase Synchronous Buck or Boost Controller |
| Pages / Page | 36 / 9 — PIN FUNCTIONS SNSD1+/SNSD2+(Pins 15 and 46):. BUCK (Pin 16):. DRVCC (Pin … |
| Revision | B |
| File Format / Size | PDF / 1.6 Mb |
| Document Language | English |
PIN FUNCTIONS SNSD1+/SNSD2+(Pins 15 and 46):. BUCK (Pin 16):. DRVCC (Pin 29):. ILIM (Pin 17):. RUN (Pin 18):. VHIGH (Pin 31):
Model Line for this Datasheet
Text Version of Document
LTC3871/LTC3871-1
PIN FUNCTIONS SNSD1+/SNSD2+(Pins 15 and 46):
DC Positive Current LDO bypasses the internal LDO powered from VHIGH. In Sense Comparator Inputs. These inputs amplify the DC applications where the supply EXTVCC is connected to is portion of the current signal to the IC’s current comparator. expected to go below ground, such as VLOW, a Schottky
BUCK (Pin 16):
The voltage on this pin determines if the diode on the pin and a 10Ω resistor in between and the IC is regulating the V external supply is strongly recommended. LOW or VHIGH voltage/current. Float or tie this pin to V5 for buck mode operation. Ground this
DRVCC (Pin 29):
Gate Driver Current Supply LDO Output. pin for boost mode operation. The voltage on this pin can be set from 6V to 10V in 1V
ILIM (Pin 17):
Current Comparator Sense Voltage Limit increments. Bypass this pin to PGND with a minimum of Selection Pin. The input impedance of this pin is 100kΩ. 4.7µF low ESR tantalum or ceramic capacitor.
RUN (Pin 18):
Enable Control Input. A voltage above
VHIGH (Pin 31):
Main VHIGH supply. Bypass this pin to 1.22V turns on the IC. There is a 2µA pull-up current on PGND with a capacitor (0.1µF to 1µF) this pin. Once the RUN pin rises above the 1.22V thresh-
PGATE (Pin 33):
Gate Drive for Input Short Protection. If old the pull-up current increases to 6µA. a UVHIGH fault is detected, PGATE drives the gate of an
FAULT (Pin 19):
Fault Indicator Output. Open-drain output external PMOS in series with the VHIGH rail high. Signal that pulls to ground during a fault condition. swings is from VHIGH to VHIGH –15V.
DRVSET (Pin 20):
The voltage setting on this pin pro-
CLKOUT (Pin 41):
Clock Output Pin. Use this pin to syn- grams the DRV chronize multiple LTC3871/LTC3871-1 ICs. Signal swing CC output voltage. The input impedance of this pin is 100kΩ. is from V5 to ground.
NC (Pins 21, 30, 32, 34, 40):
No Connect Pins.
SYNC (Pin 42):
Applying a clock signal to this pin causes the internal PLL to synchronize the internal oscillator to
TG1/TG2 (Pins 22 and 39):
Top Gate Driver Outputs. This the clock signal. The PLL compensation network is inte- is the output of the floating driver with a voltage swing grated onto the IC. This pin has a 100k internal resistor equal to DRVCC superimposed on the SW voltage. to ground.
SW1/SW2 (Pins 23 and 38):
Switch Node Connections to
FREQ (Pin 43):
Frequency Set Pin. A resistor between this the Inductors. Voltage swing at this pin is from a Schottky pin and SGND sets the switching frequency. diode (external) voltage drop below ground to VHIGH.
MODE (Pin 44):
Tying this pin to SGND enables forced
BOOST1/BOOST2 (Pins 24 and 37):
Boosted Floating continuous mode in buck or boost modes. Floating this Driver Supplies. The (+) terminal of the bootstrap capaci- pin results in discontinuous mode when in buck mode tor connects to this pin. This pin swings from a diode drop and forced continuous mode in boost mode. Tying this below DRVCC up to VHIGH+DRVCC. pin to V5 enables discontinuous mode in buck mode and
BG1/BG2 (Pins 25 and 36):
Bottom Gate Driver Outputs. non-synchronous operation in boost mode. The input This pin drives the gate(s) of the bottom N-channel impedance of this pin is 50kΩ. MOSFET(s) between PGND and DRVCC.
PHSMD (Pin 45):
Phase Mode Pin. This pin selects
PGND1/PGND2 (Pins 26 and 35):
Power Ground Pin. CH1 – CH2 and CH1 – CLKOUT phasing. Connect this pin closely to the source(s) of the bottom
GND (Exposed Pad Pin 49):
Ground. Must be soldered N-channel MOSFET(s), the (–) terminal of CDRVCC and to PCB ground for rated thermal performance. Connect (–) terminal of CVHIGH. this pin closely to the sources of the bottom N-channel
EXTV
MOSFETs and negative terminal of V
CC (Pin 27):
External Power Input to an Internal HIGH, DRVCC, V5 LDO Connected to DRV bypass capacitors. All small signal components and CC. When the voltage on this pin is greater than the DRV compensation components should connect here. Signal CC LDO setting minus 500mV, this ground pin should be connected to this exposed pad.Rev. B For more information www.analog.com 9 Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Order Information Pin Configuration Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Operation Applications Information Package Description Revision History Typical Application Related Parts
PIN FUNCTIONS SNSD1+/SNSD2+(Pins 15 and 46):
DC Positive Current LDO bypasses the internal LDO powered from VHIGH. In Sense Comparator Inputs. These inputs amplify the DC applications where the supply EXTVCC is connected to is portion of the current signal to the IC’s current comparator. expected to go below ground, such as VLOW, a Schottky
BUCK (Pin 16):
The voltage on this pin determines if the diode on the pin and a 10Ω resistor in between and the IC is regulating the V external supply is strongly recommended. LOW or VHIGH voltage/current. Float or tie this pin to V5 for buck mode operation. Ground this
DRVCC (Pin 29):
Gate Driver Current Supply LDO Output. pin for boost mode operation. The voltage on this pin can be set from 6V to 10V in 1V
ILIM (Pin 17):
Current Comparator Sense Voltage Limit increments. Bypass this pin to PGND with a minimum of Selection Pin. The input impedance of this pin is 100kΩ. 4.7µF low ESR tantalum or ceramic capacitor.
RUN (Pin 18):
Enable Control Input. A voltage above
VHIGH (Pin 31):
Main VHIGH supply. Bypass this pin to 1.22V turns on the IC. There is a 2µA pull-up current on PGND with a capacitor (0.1µF to 1µF) this pin. Once the RUN pin rises above the 1.22V thresh-
PGATE (Pin 33):
Gate Drive for Input Short Protection. If old the pull-up current increases to 6µA. a UVHIGH fault is detected, PGATE drives the gate of an
FAULT (Pin 19):
Fault Indicator Output. Open-drain output external PMOS in series with the VHIGH rail high. Signal that pulls to ground during a fault condition. swings is from VHIGH to VHIGH –15V.
DRVSET (Pin 20):
The voltage setting on this pin pro-
CLKOUT (Pin 41):
Clock Output Pin. Use this pin to syn- grams the DRV chronize multiple LTC3871/LTC3871-1 ICs. Signal swing CC output voltage. The input impedance of this pin is 100kΩ. is from V5 to ground.
NC (Pins 21, 30, 32, 34, 40):
No Connect Pins.
SYNC (Pin 42):
Applying a clock signal to this pin causes the internal PLL to synchronize the internal oscillator to
TG1/TG2 (Pins 22 and 39):
Top Gate Driver Outputs. This the clock signal. The PLL compensation network is inte- is the output of the floating driver with a voltage swing grated onto the IC. This pin has a 100k internal resistor equal to DRVCC superimposed on the SW voltage. to ground.
SW1/SW2 (Pins 23 and 38):
Switch Node Connections to
FREQ (Pin 43):
Frequency Set Pin. A resistor between this the Inductors. Voltage swing at this pin is from a Schottky pin and SGND sets the switching frequency. diode (external) voltage drop below ground to VHIGH.
MODE (Pin 44):
Tying this pin to SGND enables forced
BOOST1/BOOST2 (Pins 24 and 37):
Boosted Floating continuous mode in buck or boost modes. Floating this Driver Supplies. The (+) terminal of the bootstrap capaci- pin results in discontinuous mode when in buck mode tor connects to this pin. This pin swings from a diode drop and forced continuous mode in boost mode. Tying this below DRVCC up to VHIGH+DRVCC. pin to V5 enables discontinuous mode in buck mode and
BG1/BG2 (Pins 25 and 36):
Bottom Gate Driver Outputs. non-synchronous operation in boost mode. The input This pin drives the gate(s) of the bottom N-channel impedance of this pin is 50kΩ. MOSFET(s) between PGND and DRVCC.
PHSMD (Pin 45):
Phase Mode Pin. This pin selects
PGND1/PGND2 (Pins 26 and 35):
Power Ground Pin. CH1 – CH2 and CH1 – CLKOUT phasing. Connect this pin closely to the source(s) of the bottom
GND (Exposed Pad Pin 49):
Ground. Must be soldered N-channel MOSFET(s), the (–) terminal of CDRVCC and to PCB ground for rated thermal performance. Connect (–) terminal of CVHIGH. this pin closely to the sources of the bottom N-channel
EXTV
MOSFETs and negative terminal of V
CC (Pin 27):
External Power Input to an Internal HIGH, DRVCC, V5 LDO Connected to DRV bypass capacitors. All small signal components and CC. When the voltage on this pin is greater than the DRV compensation components should connect here. Signal CC LDO setting minus 500mV, this ground pin should be connected to this exposed pad.Rev. B For more information www.analog.com 9 Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Order Information Pin Configuration Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Operation Applications Information Package Description Revision History Typical Application Related Parts
