Datasheet ADP1872, ADP1873 (Analog Devices) - 6

ManufacturerAnalog Devices
DescriptionSynchronous Current-Mode with Constant On-Time, PWM Buck Controller
Pages / Page40 / 6 — ADP1872/ADP1873. Data Sheet. PIN CONFIGURATION AND FUNCTION DESCRIPTIONS. …
RevisionB
File Format / SizePDF / 1.7 Mb
Document LanguageEnglish

ADP1872/ADP1873. Data Sheet. PIN CONFIGURATION AND FUNCTION DESCRIPTIONS. VIN. 10 BST. COMP/EN. ADP1872. DRVH. TOP VIEW. GND

ADP1872/ADP1873 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS VIN 10 BST COMP/EN ADP1872 DRVH TOP VIEW GND

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ADP1872/ADP1873 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS VIN 1 10 BST COMP/EN 2 9 SW ADP1872 FB 3 8 DRVH TOP VIEW GND (Not to Scale) 4 7 PGND
003
VDD 5 6 DRVL
08297- Figure 3. Pin Configuration
Table 4. Pin Function Descriptions Pin No. Mnemonic Description
1 VIN High Input Voltage. Connect VIN to the drain of the upper-side MOSFET. 2 COMP/EN Output of the Internal Error Amplifier/IC Enable. When this pin functions as EN, applying 0 V to this pin disables the IC. 3 FB Noninverting Input of the Internal Error Amplifier. This is the node where the feedback resistor is connected. 4 GND Analog Ground Reference Pin of the IC. All sensitive analog components should be connected to this ground plane (see the Layout Considerations Section). 5 VDD Bias Voltage Supply for the ADP1872/ADP1873 Controller (Includes the Output Gate Drivers). A bypass capacitor of 1 µF directly from this pin to PGND and a 0.1 µF across VDD and GND are recommended. 6 DRVL Drive Output for the External Lower Side, N-Channel MOSFET. This pin also serves as the current-sense gain setting pin (see Figure 68). 7 PGND Power GND. Ground for the lower side gate driver and lower side, N-channel MOSFET. 8 DRVH Drive Output for the External Upper Side, N-Channel MOSFET. 9 SW Switch Node Connection. 10 BST Bootstrap for the Upper Side MOSFET Gate Drive Circuitry. An internal boot rectifier (diode) is connected between VDD and BST. A capacitor from BST to SW is required. An external Schottky diode can also be connected between VDD and BST for increased gate drive capability. Rev. B | Page 6 of 40 Document Outline Features Applications Typical Applications Circuit General Description Revision History Specifications Absolute Maximum Ratings Thermal Resistance Boundary Condition ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics ADP1872/ADP1873 Block Digram Theory of Operation Startup Soft Start Precision Enable Circuitry Undervoltage Lockout Thermal Shutdown Programming Resistor (RES) Detect Circuit Valley Current-Limit Setting Hiccup Mode During Short Circuit Synchronous Rectifier Power Saving Mode (PSM) Version (ADP1873) Timer Operation Pseudo-Fixed Frequency Applications Information Feedback Resistor Divider Inductor Selection Output Ripple Voltage (ΔVRR) Output Capacitor Selection Compensation Network Output Filter Impedance (ZFILT) Error Amplifier Output Impedance (ZCOMP) Error Amplifier Gain (GM) Current-Sense Loop Gain (GCS) Crossover Frequency Efficiency Consideration Channel Conduction Loss MOSFET Driver Loss MOSFET Switching Loss Body Diode Conduction Loss Inductor Loss Input Capacitor Selection Thermal Considerations Design Example Input Capacitor Inductor Current Limit Programming Output Capacitor Feedback Resistor Network Setup Compensation Network Loss Calculations External Component Recommendations Layout Considerations IC Section (Left Side of Evaluation Board) Power Section Differential Sensing Typical Application Circuits Dual-Input, 300 kHz High Current Application Circuit Single-Input, 600 kHz Application Circuit Dual-Input, 300 kHz High Current Application Circuit Outline Dimensions Ordering Guide