Datasheet ADP1828 (Analog Devices) - 9

Data Sheet ADP1828 QSOP LSCSP Pin No. Pin No. Mnemonic Description
19 17 CLKSET Clock Set Input. Setting CLKSET to logic high (connect CLKSET to VREG) sets the CLKOUT to 2× the internal oscillator frequency and is in phase with the oscillator. Setting CLKSET to logic low sets the CLKOUT to 1× the oscillator frequency and 180° out of phase. 20 18 CLKOUT Clock Output. The CLKOUT frequency, fCLKOUT, is either 1× or 2× the oscillator frequency. CLKOUT can 0be used to synchronize another ADP1828 or ADP1829 controllers. Set fCLKOUT to 1× when synchronizing another ADP1828, or to 2× when synchronizing the ADP1829. If SYNC is used, fSYNC = fCLKOUT independent of the CLKSET voltage. CLKOUT is able to drive a 100 pF load. N/A1 EPAD EPAD Exposed Pad. Connect the bottom exposed pad of the LFCSP package to system AGND plane. 1 N/A means not applicable. Rev. E | Page 9 of 33 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION SIMPLIFIED BLOCK DIAGRAM PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION INPUT POWER INTERNAL LINEAR REGULATOR SOFT START ERROR AMPLIFIER CURRENT-LIMIT SCHEME MOSFET DRIVERS SETTING THE OUTPUT VOLTAGE SWITCHING FREQUENCY CONTROL AND SYNCHRONIZATION COMPENSATION POWER-GOOD INDICATOR THERMAL SHUTDOWN SHUTDOWN CONTROL TRACKING APPLICATION INFORMATION SELECTING THE INPUT CAPACITOR OUTPUT LC FILTER SELECTING THE MOSFETS SETTING THE CURRENT LIMIT ACCURATE CURRENT-LIMIT SENSING FEEDBACK VOLTAGE DIVIDER COMPENSATING THE VOLTAGE MODE BUCK REGULATOR Type II Compensator Type III Compensator SOFT START SWITCHING NOISE AND OVERSHOOT REDUCTION VOLTAGE TRACKING COINCIDENT TRACKING RATIOMETRIC TRACKING THERMAL CONSIDERATIONS PCB LAYOUT GUIDELINE RECOMMENDED COMPONENT MANUFACTURERS APPLICATION CIRCUITS OUTLINE DIMENSIONS ORDERING GUIDE