Datasheet SLG46824 (Dialog Semiconductor) - 7
| Manufacturer | Dialog Semiconductor |
| Description | GreenPAK Programmable Mixed-signal Matrix with In System Programmability |
| Pages / Page | 171 / 7 — SLG46824. GreenPAK Programmable Mixed-Signal Matrix with In System … |
| File Format / Size | PDF / 2.8 Mb |
| Document Language | English |
SLG46824. GreenPAK Programmable Mixed-Signal Matrix with In System Programmability. Block Diagram. IO12. IO11. IO14. IO13. ACMP0L
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SLG46824 GreenPAK Programmable Mixed-Signal Matrix with In System Programmability 1 Block Diagram IO12 IO11 IO14 IO13 ACMP0L ACMP1L V
DD
IO10 In-System I2C Serial Multiple Time POR Programmability Communication Programmable Memory IO0 FILTER Combination Function Macrocells Programmable IO9 with Edge Delay or Edge Vref Out Detect Detect 2-bit 2-bit 2-bit 2-bit LUT2_0 LUT2_1 LUT2_2 LUT2_3 or DFF0 or DFF1 or DFF2 or PGen IO1 3bit 3-bit 3-bit 3-bit VDD2 Low Power Low LUT3_0 LUT3_1 LUT3_2 LUT3_3 Analog Power or DFF3 or DFF4 or DFF5 or DFF6 Vref 3-bit 3-bit 3-bit LUT3_6 LUT3_4 LUT3_5 or Pipe Delay or DFF7 or DFF8 or Ripple IO2 CNT ACMP0L ACMP1L IO8 Multi-Function Macrocells 3-bit LUT3_7 3-bit LUT3_8 3-bit LUT3_9 3-bit LUT3_10 IO3 IO7 Oscillators /DFF10+8bit /DFF11+8bit /DFF12+8bit /DFF13+8bit CNT/DLY1 CNT/DLY2 CNT/DLY3 CNT/DLY4 OSC0 OSC1 OSC2 2.048 2.048 25 3-bit 3-bit 3-bit 4-bit LUT4_0 kHz MHz MHz LUT3_11 LUT3_12 LUT3_13 /DFF9+ /DFF14+8bit /DFF15+8bit /DFF16+8bit 16bit CNT/DLY5 CNT/DLY6 CNT/DLY7 CNT/DLY0 IO4 GND IO5 SCL SDA IO6 Figure 1: Block Diagram Datasheet Revision 3.10 10-Mar-2020
CFR0011-120-00 7 of 171 © 2020 Dialog Semiconductor Document Outline General Description Key Features Applications 1 Block Diagram 2 Pinout 2.1 Pin Configuration - STQFN- 20L 2.2 Pin Configuration - TSSOP-20L 3 Characteristics 3.1 Absolute Maximum Ratings 3.2 Electrostatic Discharge Ratings 3.3 Recommended Operating Conditions 3.4 Electrical Characteristics 3.5 Timing Characteristics 3.6 OSC Characteristics 3.6.1 OSC Specifications 3.6.2 OSC Power-On Delay 3.7 ACMP Specifications 4 User Programmability 5 IO Pins 5.1 IO Pins 5.2 GPIO Pins 5.3 GPO Pins 5.4 GPI Pins 5.5 Pull-Up/Down Resistors 5.6 Fast Pull-up/down during Power-up 5.7 I2C Mode IO Structure (VDD or VDD2) 5.7.1 I2C Mode Structure (for SCL and SDA) 5.8 Matrix OE IO Structure (VDD or VDD2) 5.8.1 Matrix OE IO Structure (for IOs 1, 4, 5 with VDD, and IOs 8, 9, 10, 11, 12, 13, 14 with VDD2) 5.9 Register OE IO Structure (VDD or VDD2) 5.9.1 Register OE IO Structure (for IOs 0, 2, 3 with VDD) 5.10 Register OE IO Structure (VDD or VDD2) 5.10.1 Register OE IO Structure (for IO 6 with VDD, and IO 7 with VDD2) 5.11 IO Typical Performance 6 Connection Matrix 6.1 Matrix Input Table 6.2 Matrix Output Table 6.3 Connection Matrix Virtual Inputs 6.4 Connection Matrix Virtual Outputs 7 Combination Function Macrocells 7.1 2-Bit LUT or D Flip-Flop Macrocells 7.1.1 2-Bit LUT or D Flip-Flop Macrocell Used as 2-Bit LUTT 7.1.2 Initial Polarity Operations 7.2 2-bit LUT or Programmable Pattern Generator 7.2.1 2-Bit LUT or PGen Macrocell Used as 2-Bit LUT 7.3 3-Bit LUT or D Flip-Flop with Set/Reset Macrocells 7.3.1 3-Bit LUT or D Flip-Flop Macrocells Used as 3-Bit LUTs 7.3.2 Initial Polarity Operations 7.4 3-Bit LUT or Pipe Delay/Ripple Counter Macrocell 7.4.1 3-Bit LUT or Pipe Delay Macrocells Used as 3-Bit LUT 8 Multi-Function Macrocells 8.1 3-Bit LUT or DFF/LATCH with 8-Bit Counter/Delay Macrocells 8.1.1 3-Bit LUT or 8-Bit CNT/DLY Block Diagrams 8.1.2 3-Bit LUT or CNT/DLYs Used as 3-Bit LUTs 8.2 CNT/DLY/FSM Timing Diagrams 8.2.1 Delay Mode CNT/DLY0 to CNT/DLY7 8.2.2 Count Mode (Count Data: 3), Counter Reset (Rising Edge Detect) CNT/DLY0 to CNT/DLY7 8.2.3 One-Shot Mode CNT/DLY0 to CNT/DLY7 8.2.4 Frequency Detection Mode CNT/DLY0 to CNT/DLY7 8.2.5 Edge Detection Mode CNT/DLY1 to CNT/DLY7 8.2.6 Delayed Edge Detection Mode CNT/DLY0 to CNT/DLY7 8.2.7 CNT/FSM Mode CNT/DLY0 8.2.8 Difference in Counter Value for Counter, Delay, One-Shot, and Frequency Detect Modes 8.3 4-Bit LUT or DFF/LATCH with 16-Bit Counter/Delay Macrocell 8.3.1 4-Bit LUT or 16-Bit CNT/DLY Block Diagram 8.3.2 4-Bit LUT or 16-Bit Counter/Delay Macrocells Used as 4-Bit LUTs 9 Analog Comparators 9.1 ACMP0L Block Diagram 9.2 ACMP1L Block Diagram 9.3 ACMP Typical Performance 10 Programmable Delay/Edge Detector 10.1 Programmable Delay Timing Diagram - Edge Detector Output 11 Additional Logic Function. Deglitch Filter 12 Voltage Reference 12.1 Voltage Reference Overview 12.2 Vref Selection Table 12.3 Vref Block Diagram 12.4 VREF Load Regulation 13 Clocking 13.1 Oscillator general description 13.2 Oscillator0 (2.048 kHz) 13.3 Oscillator1 (2.048 MHz) 13.4 Oscillator2 (25 MHz) 13.5 CNT/DLY Clock Scheme 13.6 External Clocking 13.6.1 IO0 Source for Oscillator0 (2.048 kHz) 13.6.2 IO10 Source for Oscillator1 (2.048 MHz) 13.6.3 IO8 Source for Oscillator2 (25 MHz) 13.7 Oscillators Power-On Delay 13.8 Oscillators Accuracy 14 Power-On Reset 14.1 General Operation 14.2 POR Sequence 14.3 Macrocells Output States During POR Sequence 14.3.1 Initialization 14.3.2 Power-Down 15 I2C Serial Communications Macrocell 15.1 I2C Serial Communications Macrocell Overview 15.2 I2C Serial Communications Device Addressing 15.3 I2C Serial General Timing 15.4 I2C Serial Communications Commands 15.4.1 Byte Write Command 15.4.2 Sequential Write Command 15.4.3 Current Address Read Command 15.4.4 Random Read Command 15.4.5 Sequential Read Command 15.4.6 I2C Serial Reset Command 15.5 Chip Configuration Data Protection 15.6 I2C Serial Command Register Map 15.7 I2C Additional Options 15.7.1 Reading Counter Data via I2C 15.7.2 I2C Expander 15.7.3 I2C Byte Write Bit Masking 16 Non-Volatile Memory 16.1 Serial NVM Write Operations 16.2 Serial NVM Read Operations 16.3 Serial NVM Erase Operations 17 Register Definitions 17.1 Register Map 18 Package Top Marking System Definition 18.1 STQFN 20L 2 mm x 3 mm 0.4P FCD Package 18.2 TSSOP-20 19 Package Information 19.1 Package outlines for STQFN 20L 2 mm x 3 mm 0.4P FCD 19.2 Package outlines for TSSOP 20L 173 MIL Green 19.3 STQFN and TSSOP Handling 19.4 Soldering Information 20 Ordering Information 20.1 Tape and Reel Specifications 20.2 Carrier Tape Drawing and Dimensions 20.3 STQFN-20L 20.4 TSSOP-20L 21 Layout Guidelines 21.1 STQFN 20L 2 mm x 3 mm 0.4P FCD Package 21.2 TSSOP-20 Glossary Revision History
SLG46824 GreenPAK Programmable Mixed-Signal Matrix with In System Programmability 1 Block Diagram IO12 IO11 IO14 IO13 ACMP0L ACMP1L V
DD
IO10 In-System I2C Serial Multiple Time POR Programmability Communication Programmable Memory IO0 FILTER Combination Function Macrocells Programmable IO9 with Edge Delay or Edge Vref Out Detect Detect 2-bit 2-bit 2-bit 2-bit LUT2_0 LUT2_1 LUT2_2 LUT2_3 or DFF0 or DFF1 or DFF2 or PGen IO1 3bit 3-bit 3-bit 3-bit VDD2 Low Power Low LUT3_0 LUT3_1 LUT3_2 LUT3_3 Analog Power or DFF3 or DFF4 or DFF5 or DFF6 Vref 3-bit 3-bit 3-bit LUT3_6 LUT3_4 LUT3_5 or Pipe Delay or DFF7 or DFF8 or Ripple IO2 CNT ACMP0L ACMP1L IO8 Multi-Function Macrocells 3-bit LUT3_7 3-bit LUT3_8 3-bit LUT3_9 3-bit LUT3_10 IO3 IO7 Oscillators /DFF10+8bit /DFF11+8bit /DFF12+8bit /DFF13+8bit CNT/DLY1 CNT/DLY2 CNT/DLY3 CNT/DLY4 OSC0 OSC1 OSC2 2.048 2.048 25 3-bit 3-bit 3-bit 4-bit LUT4_0 kHz MHz MHz LUT3_11 LUT3_12 LUT3_13 /DFF9+ /DFF14+8bit /DFF15+8bit /DFF16+8bit 16bit CNT/DLY5 CNT/DLY6 CNT/DLY7 CNT/DLY0 IO4 GND IO5 SCL SDA IO6 Figure 1: Block Diagram Datasheet Revision 3.10 10-Mar-2020
CFR0011-120-00 7 of 171 © 2020 Dialog Semiconductor Document Outline General Description Key Features Applications 1 Block Diagram 2 Pinout 2.1 Pin Configuration - STQFN- 20L 2.2 Pin Configuration - TSSOP-20L 3 Characteristics 3.1 Absolute Maximum Ratings 3.2 Electrostatic Discharge Ratings 3.3 Recommended Operating Conditions 3.4 Electrical Characteristics 3.5 Timing Characteristics 3.6 OSC Characteristics 3.6.1 OSC Specifications 3.6.2 OSC Power-On Delay 3.7 ACMP Specifications 4 User Programmability 5 IO Pins 5.1 IO Pins 5.2 GPIO Pins 5.3 GPO Pins 5.4 GPI Pins 5.5 Pull-Up/Down Resistors 5.6 Fast Pull-up/down during Power-up 5.7 I2C Mode IO Structure (VDD or VDD2) 5.7.1 I2C Mode Structure (for SCL and SDA) 5.8 Matrix OE IO Structure (VDD or VDD2) 5.8.1 Matrix OE IO Structure (for IOs 1, 4, 5 with VDD, and IOs 8, 9, 10, 11, 12, 13, 14 with VDD2) 5.9 Register OE IO Structure (VDD or VDD2) 5.9.1 Register OE IO Structure (for IOs 0, 2, 3 with VDD) 5.10 Register OE IO Structure (VDD or VDD2) 5.10.1 Register OE IO Structure (for IO 6 with VDD, and IO 7 with VDD2) 5.11 IO Typical Performance 6 Connection Matrix 6.1 Matrix Input Table 6.2 Matrix Output Table 6.3 Connection Matrix Virtual Inputs 6.4 Connection Matrix Virtual Outputs 7 Combination Function Macrocells 7.1 2-Bit LUT or D Flip-Flop Macrocells 7.1.1 2-Bit LUT or D Flip-Flop Macrocell Used as 2-Bit LUTT 7.1.2 Initial Polarity Operations 7.2 2-bit LUT or Programmable Pattern Generator 7.2.1 2-Bit LUT or PGen Macrocell Used as 2-Bit LUT 7.3 3-Bit LUT or D Flip-Flop with Set/Reset Macrocells 7.3.1 3-Bit LUT or D Flip-Flop Macrocells Used as 3-Bit LUTs 7.3.2 Initial Polarity Operations 7.4 3-Bit LUT or Pipe Delay/Ripple Counter Macrocell 7.4.1 3-Bit LUT or Pipe Delay Macrocells Used as 3-Bit LUT 8 Multi-Function Macrocells 8.1 3-Bit LUT or DFF/LATCH with 8-Bit Counter/Delay Macrocells 8.1.1 3-Bit LUT or 8-Bit CNT/DLY Block Diagrams 8.1.2 3-Bit LUT or CNT/DLYs Used as 3-Bit LUTs 8.2 CNT/DLY/FSM Timing Diagrams 8.2.1 Delay Mode CNT/DLY0 to CNT/DLY7 8.2.2 Count Mode (Count Data: 3), Counter Reset (Rising Edge Detect) CNT/DLY0 to CNT/DLY7 8.2.3 One-Shot Mode CNT/DLY0 to CNT/DLY7 8.2.4 Frequency Detection Mode CNT/DLY0 to CNT/DLY7 8.2.5 Edge Detection Mode CNT/DLY1 to CNT/DLY7 8.2.6 Delayed Edge Detection Mode CNT/DLY0 to CNT/DLY7 8.2.7 CNT/FSM Mode CNT/DLY0 8.2.8 Difference in Counter Value for Counter, Delay, One-Shot, and Frequency Detect Modes 8.3 4-Bit LUT or DFF/LATCH with 16-Bit Counter/Delay Macrocell 8.3.1 4-Bit LUT or 16-Bit CNT/DLY Block Diagram 8.3.2 4-Bit LUT or 16-Bit Counter/Delay Macrocells Used as 4-Bit LUTs 9 Analog Comparators 9.1 ACMP0L Block Diagram 9.2 ACMP1L Block Diagram 9.3 ACMP Typical Performance 10 Programmable Delay/Edge Detector 10.1 Programmable Delay Timing Diagram - Edge Detector Output 11 Additional Logic Function. Deglitch Filter 12 Voltage Reference 12.1 Voltage Reference Overview 12.2 Vref Selection Table 12.3 Vref Block Diagram 12.4 VREF Load Regulation 13 Clocking 13.1 Oscillator general description 13.2 Oscillator0 (2.048 kHz) 13.3 Oscillator1 (2.048 MHz) 13.4 Oscillator2 (25 MHz) 13.5 CNT/DLY Clock Scheme 13.6 External Clocking 13.6.1 IO0 Source for Oscillator0 (2.048 kHz) 13.6.2 IO10 Source for Oscillator1 (2.048 MHz) 13.6.3 IO8 Source for Oscillator2 (25 MHz) 13.7 Oscillators Power-On Delay 13.8 Oscillators Accuracy 14 Power-On Reset 14.1 General Operation 14.2 POR Sequence 14.3 Macrocells Output States During POR Sequence 14.3.1 Initialization 14.3.2 Power-Down 15 I2C Serial Communications Macrocell 15.1 I2C Serial Communications Macrocell Overview 15.2 I2C Serial Communications Device Addressing 15.3 I2C Serial General Timing 15.4 I2C Serial Communications Commands 15.4.1 Byte Write Command 15.4.2 Sequential Write Command 15.4.3 Current Address Read Command 15.4.4 Random Read Command 15.4.5 Sequential Read Command 15.4.6 I2C Serial Reset Command 15.5 Chip Configuration Data Protection 15.6 I2C Serial Command Register Map 15.7 I2C Additional Options 15.7.1 Reading Counter Data via I2C 15.7.2 I2C Expander 15.7.3 I2C Byte Write Bit Masking 16 Non-Volatile Memory 16.1 Serial NVM Write Operations 16.2 Serial NVM Read Operations 16.3 Serial NVM Erase Operations 17 Register Definitions 17.1 Register Map 18 Package Top Marking System Definition 18.1 STQFN 20L 2 mm x 3 mm 0.4P FCD Package 18.2 TSSOP-20 19 Package Information 19.1 Package outlines for STQFN 20L 2 mm x 3 mm 0.4P FCD 19.2 Package outlines for TSSOP 20L 173 MIL Green 19.3 STQFN and TSSOP Handling 19.4 Soldering Information 20 Ordering Information 20.1 Tape and Reel Specifications 20.2 Carrier Tape Drawing and Dimensions 20.3 STQFN-20L 20.4 TSSOP-20L 21 Layout Guidelines 21.1 STQFN 20L 2 mm x 3 mm 0.4P FCD Package 21.2 TSSOP-20 Glossary Revision History
