HT12A/HT12EPin DescriptionInternalPin NameI/ODescriptionConnection CMOS IN Pull-high Input pins for address A0~A7 setting A0~A7 I (HT12A) These pins can be externally set to VSS or left open NMOS TRANSMISSION GATE PROTECTION DIODE (HT12E) NMOS TRANSMISSION Input pins for address/data AD8~AD11 setting AD8~AD11 I GATE PROTECTION These pins can be externally set to VSS or left open DIODE (HT12E) Input pins for data D8~D11 setting and transmission enable, active D8~D11 I CMOS IN Pull-high low These pins should be externally set to VSS or left open (see Note) DOUT O CMOS OUT Encoder data serial transmission output Latch/Momentary transmission format selection pin: L/M I CMOS IN Pull-high Latch: Floating or VDD Momentary: VSS TE I CMOS IN Pull-high Transmission enable, active low (see Note) OSC1 I OSCILLATOR 1 Oscillator input pin OSC2 O OSCILLATOR 1 Oscillator output pin X1 I OSCILLATOR 2 455kHz resonator oscillator input X2 O OSCILLATOR 2 455kHz resonator oscillator output VSS I ¾ Negative power supply, ground VDD I ¾ Positive power supply Note: D8~D11 are all data input and transmission enable pins of the HT12A. TE is a transmission enable pin of the HT12E. Approximate Internal Connections N M O S C M O S I N T R A N S M I S S I O N P u l - h i g h C M O S O U T O S C I L L A T O R 1 G A T E E N O S C 2 O S C 1 O S C I L L A T O R 2 N M O S T R A N S M I S S I O N G A T E P R O T E C T I O N D I O D E X 1 X 2 V D D Rev. 1.20 3 February 20, 2009 Document Outline Features Applications General Description Selection Table Block Diagram Pin Assignment Pin Description Absolute Maximum Ratings Electrical Characteristics Functional Description Application Circuits Package Information Product Tape and Reel Specifications